Samsung Showcases 3D Stacked Transistor Research Results
Alina Collins
Samsung unveiled a transistor architecture that stacks devices vertically instead of laying them side by side, achieving a 42-nanometer gate pitch — the paper won Best Paper at the 2026 VLSI Symposium, pointing to a new path for packing more transistors without enlarging the chip.
What exactly did Samsung build?
Samsung's semiconductor research center demonstrated a 3D Stacked FET (field-effect transistor) architecture — stacking n-type and p-type transistors vertically rather than placing them side by side on a flat plane.
In plain terms = two transistors that used to sit next to each other now sit on top of each other, halving the footprint.
The prototype uses a 42-nanometer gate pitch with three nanosheet channels to maintain current flow, plus advanced epitaxial growth to keep the silicon layers uniform.
The paper was presented at the 2026 VLSI Symposium and received Best Paper and Technology Highlight honors.
Why stack transistors vertically?
The traditional approach — shrinking transistors on a flat surface — is running into physical limits; each new generation yields diminishing returns.
This means → the industry needs a new dimension to keep Moore's Law alive, shifting from "shrink smaller" to "stack higher."
Samsung emphasized that 3D stacking is an evolution of its existing GAA (gate-all-around — a transistor design where the gate wraps around the channel from all sides) technology, not a replacement.
Put simply = GAA's nanosheet structure is naturally suited to vertical integration, which is what makes this path viable.
How is the isolation problem solved?
Once transistors are stacked, electrical interference between the upper and lower layers becomes the central challenge.
Samsung's answer is a mid-level dielectric isolation (MDI) structure — an insulating layer inserted between the two vertically stacked transistors to block electrical crosstalk.
This means → the two transistors are physically touching yet electrically independent — a prerequisite for the stacked architecture to function.
Where does this stand competitively — and how far from production?
Samsung was the first to mass-produce GAA transistors in 2022, maintaining a first-mover pace on architecture evolution; TSMC and Intel are advancing their own next-generation transistor designs.
Samsung said the successful 42 nm gate-pitch demonstration provides a technical foundation for future AI, high-performance computing, and mobile processors.
The technology, however, remains at the research stage — volume production is still some distance away.
This reflects a common industry rhythm: the gap between a lab paper and factory-scale production often spans years, and when this converts into an actual process node will be the key milestone to watch.
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