Google's Next-Gen TPU Switches to Intel EMIB-T Packaging
Claire Weston
Google's next TPU, codenamed Humufish, will drop TSMC's CoWoS in favor of Intel's EMIB-T packaging — the first flagship AI chip from a top tech company to publicly break from CoWoS, directly challenging TSMC's monopoly in advanced packaging.
Why is Google switching packaging vendors?
SemiAnalysis disclosed on July 1 that Google's next-gen TPU, codenamed Humufish, will use Intel's EMIB-T instead of TSMC's CoWoS.
This means → a top tech company's flagship AI chip is publicly moving away from CoWoS for the first time — a signal far bigger than a single customer switching suppliers.
CoWoS — a packaging method that places multiple chips on one large silicon interposer to connect them — has long been the industry's default. Google just became the first major player to break ranks.
What makes EMIB-T better than CoWoS?
CoWoS requires a single large interposer — silicon or RDL — to carry all dies. Its physical size is capped by the reticle limit; the single-panel CoWoS-S tops out at roughly 3.3× reticle size.
Intel's EMIB takes a fundamentally different approach: tiny silicon bridges are embedded directly in an organic substrate, placed only where chip-to-chip links are needed. No reticle ceiling, better scalability.
In plain terms = CoWoS lays one giant carpet and puts the furniture on top — the carpet has a size limit. EMIB lays narrow walkways only between pieces of furniture, as long as needed.
EMIB also eliminates the expensive interposer entirely. The bridges are small, tightly packed, and waste little material — packaging cost drops significantly versus CoWoS.
What does the "T" in EMIB-T solve?
"T" stands for TSV — through-silicon via, a vertical channel punched through silicon to deliver power. Standard EMIB routes power around the bridge through the substrate — a longer, lossier path.
EMIB-T sends power vertically through the bridge itself, adding capacitors and ground planes for cleaner delivery.
This means → it is an upgrade designed specifically for next-gen HBM and higher-bandwidth interconnects — the power density that standard EMIB cannot deliver, EMIB-T can.
Why does Humufish fit EMIB particularly well?
Independent analyst Nutty notes that CoWoS-L adds a global RDL routing layer above its silicon bridges — more flexible wiring, but larger area, greater process complexity, and higher cost.
Humufish is optimized for inference and AI-agent workloads. Its data flows are more regular and structured.
In plain terms = if data flows run like fixed bus routes, EMIB only needs dedicated lanes between stops — no reason to pay extra for "go anywhere" routing flexibility.
What is the biggest risk?
SemiAnalysis warns: standard EMIB has shipped at scale for years, but EMIB-T is new technology. Power-delivering silicon bridges are harder to manufacture at volume.
This means → Intel's yield and delivery pace are the single largest unknown in the entire plan.
If Intel slips, Google's fallback is still capacity-constrained CoWoS — this reflects a hedge, not an all-in bet: Google is balancing "better cost-performance" against "supply-chain safety."
What does this mean for the industry landscape?
TSMC's CoWoS has held a near-monopoly in AI chip packaging; its capacity crunch is an industry-wide bottleneck.
Google's shift to EMIB-T is the first substantive challenge to that monopoly — if Humufish ramps smoothly, other major customers may follow.
This reflects a deeper shift: the AI compute race's bottleneck is moving from chip design to packaging. Whoever offers the better packaging solution wins the next round of orders.
Content is for reference only, not financial advice.