CXMT Tests Bonded DRAM Production Line, China-Korea Gap Narrows to About Three Years
Miles Bennett
CXMT is secretly testing a bonded-DRAM pilot line in Hefei, aiming to mass-produce high-performance DRAM without EUV lithography — the China-Korea DRAM technology gap has shrunk from roughly five years to about three, far faster than the industry expected.
What is bonded DRAM, and why does it sidestep EUV?
Bonded DRAM fabricates the memory-cell array and the peripheral circuits on two separate wafers, then bonds them vertically. In plain terms = ordinary DRAM writes data cells and circuits on one sheet; bonded DRAM draws each on its own sheet and glues them together.
This means → each layer needs only the less precise DUV lithography — deep-ultraviolet tools CXMT already owns — with multi-patterning. No sanctioned EUV equipment required.
Samsung is pursuing the same idea under its "B1b" project; SK hynix is also following. Yet Korean media, citing industry assessments, say CXMT may already lead both Korean rivals in the technology itself and in development speed.
How did the gap shrink from five years to three?
Two years ago CXMT (DRAM) and YMTC (NAND) were loss-making and could only produce low-end chips. Korean media now call the turnaround "dramatic."
This means → U.S. export controls blocked EUV access but inadvertently forced a non-EUV development path whose progress has been "far faster than expected."
On market share, CXMT's global DRAM share rose to 8% in Q1 2026. The company is reportedly being evaluated by Apple as a potential new supplier.
Where does CXMT stand on HBM and "post-HBM"?
CXMT has shifted roughly 20% of its capacity toward HBM3/HBM3E — high-bandwidth memory, the fast "video RAM" AI chips require — again using DUV multi-patterning to bypass EUV.
It is also partnering with Montage Technology to develop "post-HBM" memory based on the CXL protocol — a new interface standard for high-speed communication between CPUs and memory.
This means → CXMT is not just chasing today's HBM; it is betting on next-generation interconnected memory, leveraging its DDR5 R&D experience to stake out an early position.
How large is YMTC's patent advantage?
YMTC's proprietary "Xtacking" wafer-bonding architecture was the world's first commercialized technology of its kind, scaling from 160 layers to the latest 270-layer mass production.
Core patent comparison (2023 data): YMTC 119 / Samsung 83 / SK hynix just 11.
Korean media report that Samsung has licensed patents from YMTC for its next-generation NAND roadmap. This reflects a shift in patent leverage toward China in this specific segment.
What are Korean academics saying?
Seoul National University professor Hwang Chul-sung called Chinese semiconductors "Korea's greatest future threat," warning that once Huawei and other Chinese AI-chip makers adopt domestic memory at scale, yield and reliability could improve faster than expected.
Other scholars argue Korea must build an insurmountable lead in next-gen memory and packaging before the "golden window" created by U.S. sanctions closes.
In plain terms = sanctions bought Korea time, but the window is closing — if the incumbents do not open a generational gap now, the chasers will arrive before it shuts.
IPO and mass production — what to watch next?
Both CXMT and YMTC are advancing IPO plans. CXMT could list on the Shanghai Stock Exchange as early as this month, broadening its funding beyond government subsidies.
Whether the bonded-DRAM pilot line progresses to mass production on schedule is the critical checkpoint for judging if this catch-up narrative holds.
This means → whether capital markets can keep pace and lab results can reach the fab floor will determine if the "three-year gap" keeps narrowing — or stalls where it is.
Content is for reference only, not financial advice.