Samsung and SK Hynix Delay Hybrid Bonding Adoption for HBM
Claire Weston
Samsung and SK Hynix have both pushed back hybrid bonding adoption in HBM, now targeting HBM4E at the earliest — possibly later. This means the existing TC bonding process gets a longer runway, and capex timelines for hybrid-bonding equipment and materials shift out accordingly.
Why was hybrid bonding pushed back?
Both companies originally planned to introduce hybrid bonding — a process that joins chip layers directly through copper pads, eliminating solder bumps — at HBM4 (6th-gen). Instead, they stuck with conventional TC bonding (thermo-compression bonding, which melts solder bumps under heat to connect layers).
The new target is 16-layer HBM4E (7th-gen), and some industry insiders say the actual timeline could slip further.
This means → equipment and materials suppliers positioned around hybrid bonding face a longer wait for revenue, and near-term capex plans need recalibrating.
Why can TC bonding keep going — what changed on thickness?
HBM thickness standards are loosening: HBM3E was set at 720 µm, HBM4 moved to 775 µm, and JEDEC is now discussing raising the ceiling for 20-layer HBM5 from 900 µm to roughly 1,000 µm.
In plain terms = a higher thickness ceiling means layers don't need to be squeezed to the limit. TC bonding's bump structures still fit, so the technical pressure eases.
At the same time, key customers like Nvidia have pushed back their own timelines for high-stack HBM. An industry source noted: even within HBM4E, 12-layer products will likely remain dominant — discussions around 16-layer are quiet.
Can the thermal problem be solved without hybrid bonding?
Better heat dissipation was a key selling point of hybrid bonding, but both companies have developed standalone alternatives: Samsung's HPB (Heat Path Block) and SK Hynix's iHBM (ICE HBM), both now being tested for HBM5.
Packaging industry sources say placing thermal components next to HBM dies is not technically difficult and faces no commercialization barriers.
This reflects a weakening of hybrid bonding's "irreplaceability" on the thermal front — memory makers now have a safer bridge solution.
Will hybrid bonding still arrive — and what's the real trigger?
HBM4 doubled I/O count from HBM3E's 1,024 to 2,048. TC bonding's solder bumps spread laterally when melted, making it hard to support even denser I/O.
The industry is discussing another doubling to 4,096 I/Os from HBM5E onward. At that pitch, hybrid bonding becomes a necessity.
Put simply = hybrid bonding isn't abandoned — it's deferred. Its real commercial window depends on when I/O density hits TC bonding's physical wall. Until then, the old process can carry a few more generations.
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