Bernstein: Huawei's Tao Law is China's Semiconductor 'DeepSeek Moment'

Huawei proposed "Tao's Law" at the ISCAS 2026 conference on May 25, with the core proposition of using the time scale of compressed signal delays to replace the traditional geometric scaling that relies on reducing transistor sizes, as a new evolutionary framework for the post-Moore era. Bernstein immediately released a research report, believing that this breakthrough is comparable to the catalytic significance of DeepSeek for the AI industry chain, and reiterated the "outperforming the market" rating for China's semiconductor sector.

After the announcement, the A-share semiconductor sector responded strongly, with the STAR 50 Index closing up 5.9% on the day. Bernstein pointed out that Tao's Law proves that China can still achieve important technological progress under export control environments, and provides a systematic solution for continuous iteration of chip performance while bypassing EUV lithography.

LogicFolding: From chip stacking to element stacking

One of the technical pillars of Tao's Law is Huawei's self-developed LogicFolding solution. On the surface, the technology is similar to TSMC's SoIC, both using vertical chip stacking architecture, but Huawei has achieved a hybrid bonding spacing of less than 2 microns, enabling the logic circuit to be stacked at the element level rather than the traditional chip level, thereby directly compressing the signal transmission delay between adjacent transistors.

This path also brings a dual increase in density and frequency. According to Huawei's roadmap, the number of transistors that can be accommodated on a chip of the same area will increase from about 155 million per square millimeter in 2025 to about 238 million in 2026, roughly catching up with TSMC's 3-nanometer node density level. By 2031, the goal is to double to more than 400 million, benchmarking the density of TSMC's most advanced process.

Bernstein reminds that the density data for 2026 may be based on the superimposed calculation of two chips, and is not directly comparable to TSMC's single-chip indicators.

System-level optimization: Targeting a 125-fold increase in computing power within five years

Another key dimension of Tao's Law is system-level delay compression. Huawei proposes to use near-chip optical interconnect technology Hi-ONE and a unified bus network architecture to compress cluster communication delay from the tens of microseconds level to about 100 nanoseconds, achieving a reduction of about 500 times.

Based on the collaborative improvements at the chip and system levels, Huawei has set a goal of increasing the total computing power of supercomputing Pods by 125 times before 2030, corresponding to an average annual compound growth rate of about 3.3 times.

Realistic constraints: The gap still exists

Bernstein's assessment of Tao's Law is not blindly optimistic. The research report points out three constraints: Tao's Law heavily depends on the continuous breakthroughs in 3D advanced packaging, and TSMC still has a significant lead in this field; the power density and heat dissipation issues brought by multi-chip stacking require innovations in power transmission to solve; whether the yield and cost can support mass production is also unknown.

The analyst believes that the global competitors can also follow the technological direction introduced by Huawei, and Huawei will still not be able to obtain EUV equipment in the short term, so China's semiconductors will still lag behind in absolute terms. However, these innovations are expected to support continuous improvement and gradually narrow the gap with the leaders.

Industry chain catalysis: Foundry, equipment, AI chip benefits across the board

Bernstein compares the industrial impact of Tao's Law to DeepSeek on AI, the latter of which has promoted the localization of China's full-stack AI investment, and the former is expected to stimulate the confidence of domestic replacement in the entire semiconductor industry chain. The research report most favors SMIC, North Microelectronics, and TuGeng Technology in three directions, respectively corresponding to advanced logic chip foundry, manufacturing equipment, and packaging bonding equipment segments.

In addition, Hua Hong Semiconductor, SinoMicro, Cambricon, and Hai Guang Information have also been rated "outperforming the market". However, Bernstein notes that while AI chip design companies benefit from a clearer path to performance improvement, they also face direct competition from Huawei, and their upward space is relatively limited.