BofA: Server CPU Demand Drives TSMC 5nm/3nm Capacity Share to 13%
Miles Bennett
BofA projects server CPU wafer consumption will triple in three years, reaching 13% of TSMC's 5nm-and-below capacity by 2028, strengthening TSMC's pricing power and prompting a target price raise to NT$3,060.
How much advanced capacity will server CPUs consume?
BofA estimates monthly server CPU wafer consumption will rise from 16,000 in 2025 to ~50,000 in 2028, lifting their share of TSMC's 5nm-and-below capacity from 6% to 13%.
This means → server CPUs are shifting from a sideshow to a major competitor with GPUs for TSMC's most advanced lines, tightening an already strained foundry market.
The driver: AI workloads are pivoting from training to inference and agentic applications, which demand heavy CPU compute alongside GPUs, pushing both CPU complexity and volumes higher.
Who is sending CPU production to TSMC?
AMD, Nvidia, and hyperscalers like Google are outsourcing server CPUs to TSMC, pushing outsourced production penetration from 52% in 2025 to 71% by 2028.
Ramp speeds are steep: AMD Venice grows from 2.8 million units in 2026 to 8.7 million in 2027; Nvidia Vera hits 9.4 million in 2027; Google Axion tops 5.5 million in 2027.
In plain terms = Intel used to manufacture most server CPUs in-house. Now AMD and hyperscaler custom chips are gaining share fast — and all of them rely on TSMC's advanced lines.
Why can TSMC keep raising prices?
TSMC's 7nm-and-below capacity will grow from 320,000 wafers per month in 2023 to ~680,000 by 2028, a 16% CAGR, with advanced nodes reaching 40%–45% of total capacity.
Even with continuous expansion, 3nm utilization stays near full load — this means → demand growth outpaces supply growth, giving TSMC sustained pricing leverage.
Margins benefit accordingly: depreciation grows at a 17% CAGR while revenue grows at 28%, and BofA projects gross margin expanding to 68% by 2028.
Where do capex and earnings estimates land?
BofA expects TSMC capex of $76 billion in 2027 and $81 billion in 2028, a 21% CAGR over 2026–2028.
Target price raised from NT$2,560 to NT$3,060 (ADR from $490 to $590), with a Buy rating maintained.
EPS estimates for 2026/2027/2028 lifted to NT$103/150/177 — this reflects BofA's conviction that the server CPU ramp will become TSMC's next earnings growth engine.
Who benefits most in packaging?
Both Nvidia Vera and AMD Venice use CoWoS packaging — an advanced method that integrates multiple chips side-by-side on one substrate. BofA estimates the server CPU packaging and testing market will grow at a 71% CAGR to $9.6 billion by 2028.
Industry CoWoS capacity needs to expand at a 52% CAGR to keep up. ASE's capacity share rises from 18% in 2026 to 29% in 2027; its LEAP business is projected to grow at a 96% CAGR to ~$12 billion by 2028.
In plain terms = chips are getting so complex that manufacturing them is only half the battle — assembling multiple chips into one package is equally constrained, and ASE is capturing a rapidly growing slice of that spend.
What comes next in 3D packaging?
AMD has validated hybrid bonding — joining two chips directly, copper-to-copper — through its 3D V-Cache roadmap. Its sixth-gen EPYC Venice will combine TSMC's SoIC-X and CoWoS-L technologies.
Nvidia plans to adopt a similar approach on its Feynman GPU by 2028. TSMC's SoIC capacity — its chip-stacking platform — is projected to grow from 20,000 wafers per month in Q4 2026 to 50,000 in Q4 2028.
This means → whether server CPUs ramp on schedule will be the key test of whether TSMC's advanced-node utilization can stay at peak levels.
Content is for reference only, not financial advice.