China Chip Equipment Makers See Record AI Orders, Backlogs Extending to 2027
nashnova research
AI infrastructure spending has pushed order backlogs at China's semiconductor equipment makers to historic highs, with several leaders booked solid through 2027 — but component-supply bottlenecks may slow the conversion of orders into revenue.
How big is the order surge?
AMEC said its 2026 new orders hit all-time highs in both value and growth rate, exceeding the revenue it booked in the same period. This means → the company is selling faster than it can deliver.
ACM Research reported a backlog of RMB 17.1 billion (≈ $2.55 bn) as of late September 2026, up 88.2% year-on-year; new orders in the first three quarters jumped 147%.
Kunshan Dongwei Technology said its equipment orders are fully booked through 2027, with new contracts concentrated in high-end models and a backlog of roughly RMB 4.5 billion.
Who is writing the cheques?
Industry group SEMI forecasts that global 300 mm fab front-end equipment spending will reach $149 billion in 2026, up 31% year-on-year, and could climb to $227 billion by 2029. In plain terms = chipmakers worldwide will nearly double their equipment budgets over three years.
AI compute expansion is accelerating capacity investment in HBM — high-bandwidth memory, stacked memory chips designed for AI workloads — and DRAM. At AMEC, DRAM-customer orders grew faster than overall orders in the first three quarters; NAND plus DRAM clients accounted for roughly 60% of total orders.
Advanced packaging — assembling multiple chips into a tighter, higher-performance unit — is pulling equipment demand in parallel. HBM and CoWoS processes are driving rising orders for wafer bonding, TSV etching (through-silicon vias, vertical channels drilled through a chip to connect stacked layers), plating, and inspection tools.
How advanced can domestic equipment get?
AMEC's ICP etch system — inductively coupled plasma etch, which uses plasma to carve ultra-fine trenches on a chip — has achieved a 140:1 high-aspect-ratio etch and has shipped to leading domestic memory fabs for qualification. This means → Chinese equipment makers are closing the gap with global leaders on a critical process step.
AMEC's tungsten deposition product line has shipped more than 500 reactor chambers and secured volume orders; a next-generation atomic-layer molybdenum deposition tool is also in qualification.
Piotech has shipped over 4,400 reactor chambers across advanced memory, logic, and packaging, with a rising share from PECVD — plasma-enhanced chemical vapor deposition, used to grow ultra-thin films on chip surfaces.
Where does advanced-packaging equipment stand?
Several of Piotech's PE-ALD systems — plasma-enhanced atomic layer deposition, which deposits material one atomic layer at a time — have passed customer qualification and are supporting memory fab expansions.
Piotech is also developing chip-to-wafer fusion bonding and bonding-interface void-repair tools; its next-generation Dione 300 eX high-speed, high-precision wafer-to-wafer hybrid bonding system has completed customer verification. In plain terms = the domestic tool for pressing two chips face-to-face has cleared the customer's test process.
NAURA Technology likewise reported strong order growth and a sharp rise in shipments, attributing the momentum to AI-driven global semiconductor demand.
Can all these orders actually turn into revenue?
Dongwei Technology posted 45.76% revenue growth to RMB 1.103 billion in the first three quarters of 2026, with net profit surging 90.88% to RMB 163 million, driven mainly by strong demand for high-end PCB plating equipment.
China's sputtering-target market — consumable materials used to deposit thin films onto wafers — was roughly RMB 3.365 billion in 2025, projected to reach RMB 3.8 billion in 2026; the global semiconductor target market could ultimately exceed $7 billion, more than double its current size.
This reflects a parallel expansion in upstream consumables, but whether the order backlog can convert smoothly into revenue once component-supply constraints ease remains the key test of this cycle's staying power.
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