Citrini: AMD's Acquisition of MEXT Bets on Flash Replacing DRAM, Memory Costs Could Drop 55x
N.R. Finch
AMD completed its acquisition of memory-optimization firm MEXT, bringing AI-driven flash optimization into the data center; Citrini Research estimates flash costs roughly $0.05 per GB — less than 1/55th of DRAM — signaling a fundamental restructuring of memory architecture for AI inference.
What capability did this acquisition actually buy?
MEXT's core technology is predictive memory optimization — making flash storage (a cheaper, higher-capacity storage chip) behave more like DRAM (a faster but far more expensive memory chip).
This means → data centers can expand usable memory capacity without relying entirely on costly DRAM, while maintaining performance.
AMD stated: "Demand for memory is growing across every category of enterprise computing." In plain terms = memory is scarce everywhere, and AMD is using software to make cheap flash do expensive memory's job.
Why did the market react so strongly?
AMD shares rose 7.7% to $550.75 on the day, pushing market cap close to $900 billion; the S&P 500 gained just 1.8% overall.
AMD is up 323% year-to-date. Citi upgraded AMD from neutral to buy last Friday, raising its target from $460 to $575.
This reflects the market pricing in an architecture-level shift — "use cheaper flash to ease the DRAM shortage" — not a minor tweak.
Why is DRAM so scarce and so expensive?
High Bandwidth Memory — HBM, ultra-fast memory designed for AI — now consumes roughly 25% of all DRAM wafer capacity, up from just 2% in 2020. This means → AI has swallowed a quarter of DRAM production lines, squeezing supply for phones, PCs, and gaming consoles.
DRAM contract prices surged roughly 90% quarter-on-quarter in Q1 2026. Xbox CEO Asha Sharma said memory costs rose about fivefold in two years, making it impossible to produce enough consoles.
In plain terms = building new DRAM capacity requires EUV lithography machines (about $200 million each), tens of billions for a new fab, and years of construction. Supply is structurally rigid; this shortage has staying power.
Why can flash replace some of this DRAM?
The key entry point is the KV cache in AI inference — the data recording all prior context as a model generates text, which can grow to hundreds of gigabytes in long conversations. This data's read-speed requirement is far lower than the decode path for model weights.
In plain terms = the KV cache is like flipping through notes — sequential reading is fine. Model weights are like high-speed computation — they need extreme access speed. The former is exactly what flash excels at.
Apple's earlier paper "LLM in a Flash" validated this path: storing model parameters in flash and loading them into DRAM on demand achieved inference speeds 20–25× faster than naive loading on GPU.
Why is flash far easier to scale than DRAM?
Flash adds capacity by stacking more cell layers vertically, using deposition and etch processes already in existing fabs. It does not need EUV lithography and does not compete for advanced-node resources.
Flash controllers are built on mature 6/7 nm nodes, far from the bottleneck constraining leading-edge chips.
This means → DRAM expansion is gated by EUV; flash expansion runs on an entirely different process track — lower cost, shorter cycle, fewer bottlenecks.
Who benefits most across the supply chain?
Citrini Research identifies NAND manufacturers as the most direct beneficiaries — high-capacity NAND, enterprise SSDs, and QLC NAND are the purest plays, involving SanDisk, Western Digital, Micron, and Kioxia.
The SSD controller layer is seen as having the strongest durability: controllers, firmware, and NVMe architecture optimization are the core of making flash truly approach a memory-like experience, involving Silicon Motion, Marvell, and others.
This reflects a clear transmission chain: AI inference memory demand overflows → shifts down from HBM/DRAM to flash/SSD → NAND makers capture volume, controller makers capture value.
Content is for reference only, not financial advice.