Fubon: Rubin Delay Doesn't Alter AI Demand — CoWoS/HBM/TPU on Three Fronts Reshaping the Semiconductor Landscape
0xBroomberg
Fubon maintains its overweight call on Taiwan tech, arguing that Nvidia's Rubin delay disrupts supply-chain revenue timing but not AI demand direction — CoWoS capacity allocation, HBM cost trajectory, and Google TPU ramp are the three lines that will define 2027–2028 industry dynamics.
CoWoS capacity — who gets the wafers gets the power?
Fubon forecasts TSMC CoWoS capacity at ~190K wafers/month by end-2027, rising to ~220K in 2028 with further upside possible. This means → TSMC is shifting resources from SoIC — a technology that stacks chips vertically — toward CoWoS — which lays chips side by side on a silicon interposer. Its Q4 2028 SoIC forecast has been cut from 43K to 20K wafers/month.
ASE's CoWoS forecast is raised to 50K wafers/month, mainly serving CPU and networking clients. In plain terms = advanced packaging is no longer TSMC's monopoly; ASE is absorbing the overflow.
On the client side, Nvidia still takes over 50% of TSMC's CoWoS output, with its 2027 allocation rising from ~62K to ~103K wafers. Broadcom ranks second; MediaTek and AMD allocations are also climbing — AMD's total may reach ~30K wafers, with most of the increase from ASE.
This reflects a deeper shift: CoWoS allocation is effectively power allocation in AI semis — no longer a single-customer Nvidia story, but a multi-client, multi-product pull.
Rubin delay — what was actually lost, and what wasn't?
Rubin Ultra's cancellation or postponement of the Kyber rack and quad-die design led Fubon to cut near-term Rubin shipments to ~1 million units. Yet 2026 total CoWoS chip output is roughly unchanged — stronger Blackwell shipments in Q3 partially offset the gap.
Fubon estimates each CoWoS wafer yields ~12 interposers for Rubin and ~10 for Rubin Ultra. Nvidia's total chip output is projected to rise from ~8.2 million in 2026 to ~12.4 million in 2027. This means → the delay shifts revenue recognition from high-ASP Rubin back to Blackwell, compressing near-term margin upside. Supply-chain names may underperform short-term, but the medium-to-long-term AI demand call is intact.
On rack architecture, Nvidia is still evaluating two alternatives: one retains the current Oberon rack with four racks linked conventionally for 576 compute dies total; the other uses a two-rack design with NPO/CPO — near-package or co-packaged optics, which place optical transceivers inside the package to shorten data paths — for scale-out connectivity. Neither is finalized, but Fubon sees Nvidia still positive on the NPO/CPO path.
HBM cost — the biggest unknown on the 2027 bill of materials?
Rubin's move to HBM4 — fourth-generation high-bandwidth memory, faster but costlier — pushes HBM costs meaningfully higher. Fubon estimates that non-Nvidia customers (GPUs and custom ASICs with less pricing power) could face HBM costs of $85–90/GB. A doubling of HBM cost in 2027 remains the single largest uncertainty in the AI server BOM.
In plain terms = who pays for the memory price hike? Fubon's view: as long as system-level performance gains keep driving per-token inference cost down, hyperscalers will not stop spending just because HBM gets more expensive. This means → token cost is the real anchor for cloud capex decisions, not any single component price.
Google TPU ramp — where is the biggest 2028 increment?
Fubon expects Google to deploy 12–15 million TPUs in 2028. The V9 generation will adopt a quad-die design, sharply increasing advanced-packaging consumption. This means → TSMC alone may not be enough; Intel's EMIB-T — a packaging technology that uses silicon bridges to link multiple chips — becomes critical supply.
The report is most constructive on ASE and MediaTek: ASE benefits from rising AMD and CPU-client allocations; MediaTek can leverage custom ASIC capabilities to gain share in a multi-client landscape.
Two key verification points for 2028: whether Google's TPU ramp stays on schedule, and whether Intel's EMIB-T yields meet the bar. This reflects a widening supply bottleneck — from "Is TSMC enough?" to "Can Intel step up?"
The big picture — how do the three lines converge?
Fubon's framework: CoWoS allocation = power distribution, HBM cost = margin elasticity, TPU ramp = incremental volume. Together, they set the rhythm of AI semiconductors through 2027–2028.
The Rubin delay is a timing disruption, not a direction reversal. Put simply = the money will still be spent; what changes is the timetable and which names receive it.
This reflects a structural shift: AI semiconductor competition has moved beyond single-GPU performance into a multi-dimensional contest over advanced-packaging capacity, system architecture, and client allocation — whoever secures CoWoS, controls HBM cost, and proves out rack-level design holds the keys from 2027 onward.
Content is for reference only, not financial advice.