Gelsinger: AI Compute Efficiency Must Improve 10,000x; Power, Storage, and Fab Constraints Prevent Linear Scaling
nashnova research
Former Intel CEO Pat Gelsinger warns that power, memory, and fab capacity form a triple constraint — AI compute efficiency must improve at least 10,000× because simply adding hardware can no longer sustain the next phase of growth.
Why can't we just build more data centers?
In 2025, US power supply grew roughly 5% — and AI workloads consumed nearly half of that new capacity.
This means → the grid is growing far too slowly for AI's expansion rate; electricity is the first hard wall.
Gelsinger's blunt math: scaling AI 10,000× under the current architecture would require a matching linear expansion of the grid, memory capacity, and fab output — physically impossible.
In plain terms = a 10% chip-performance gain or a 10% power-efficiency gain is a rounding error against a 10,000× gap. The industry needs a fundamentally different compute architecture.
What role does Taiwan play in the AI supply chain?
Gelsinger summed up Taiwan's speed in one line: "Concept in the morning, prototype by lunch, pilot production before dinner."
He sees Taiwan's ability to turn ideas into mass-produced products at speed as a non-substitutable core advantage for the global AI supply chain.
This reflects a deepening symbiosis: Taiwan's economy has accelerated visibly on AI workload growth, and the relationship now reinforces in both directions.
What is Playground Global betting on?
Gelsinger is now a partner at Playground Global, which incubates startups pushing past physical limits in memory, advanced packaging, photonics, and power delivery.
This means → the investment thesis is not "build a faster chip" — it is remove the physical bottlenecks blocking AI's next scaling phase.
What problem is the new memory startup Nagare trying to solve?
Playground Global recently launched Nagare, a memory startup targeting AI's biggest hidden constraint — memory itself.
AI is fundamentally a memory-bound workload — the larger the model, the deeper its dependence on memory bandwidth and capacity.
For roughly thirty years the industry has relied on DRAM, SRAM, and flash; manufacturing processes improved, but architectural breakthroughs have been extremely rare.
In plain terms = Nagare aims to fuse the best properties of all three memory types into one new architecture — not refining the old technology, but taking a different road entirely.
Why is advanced packaging also a critical piece?
Advanced packaging — the technology for tightly stacking and interconnecting multiple chips — is another key pillar in Playground Global's portfolio.
This means → new chip architectures alone are not enough; how chips connect and assemble determines whether compute efficiency can achieve the order-of-magnitude leap required.
Gelsinger's view: whether architectural innovation can be commercialized will be the defining variable for AI's next phase.
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