Huawei's 'Tao Strategy' Reshapes the Chip Race, Chinese Semiconductors' Full Industry Chain Faces Strategic Revaluing

The Moore's Law that has dominated the semiconductor industry for over half a century is facing a fundamental challenge from China.

Huawei has recently officially proposed a new development path for semiconductors named "τ (Tao)". According to the research notes from the electronic team at Changjiang Securities, τ is derived from the time constant in circuit theory. The core is to replace the traditional Moore's Law of geometric size reduction with temporal scaling, optimizing the total feedback time of the system signal from input to output as a target, and reconstructing the logic framework for improving chip performance from the bottom up.

This proposal did not emerge out of the blue. Since facing chip sanctions in 2019, Huawei has been forced to break away from the industry's single-path dependence on advanced processes and instead explore new directions in chip upgrades from a temporal dimension — the Tao Law is the theoretical crystallization of this exploration.

The Economic Viability of Moore's Law Has Failed

To understand the investment value of Tao's Law, one must first understand why Moore's Law has reached its end.

Physically, as the process node advances to 2 nanometers, it has approached the limit of atomic size. The electron saturation velocity effect causes marginal performance gains from size reduction to diminish; parasitic resistance and capacitance within the chip cause signal delay, becoming an invisible ceiling for performance improvement.

Economically, the cost curve has already reversed. According to data cited in the Changjiang Securities notes, the wafer costs several tens of millions of dollars for 14 nm, and it has soared to several hundred million to one billion dollars for 2 nm processes. More critically, the cost of a single transistor at 3 nm and 2 nm nodes has increased rather than decreased; the economic logic of "cheaper with more advancement" in Moore's Law is breaking down. This means that even without external sanctions, the return on investment in the traditional path is sliding systematically.

Technical Logic of Tao's Law: Folding Circuits, Vertical Victory

The core insight of Tao Law is that the signal delay caused by the metal wires connecting transistors has exceeded the switching time of the transistors themselves, becoming the real bottleneck of chip performance.

In traditional planar chips, signals spread horizontally along metal wires, and the overall performance limit of the chip is determined by the longest signal delay path (the "critical path"). Tao Law's solution is to fold the circuit - dissecting the chip into two or even three parts, stacking them vertically to connect without the need for a long horizontal distance, fundamentally compressing transmission delays.

The strategic significance of this path is that it bypasses the dependence on EUV lithography machines and advanced processes, achieving high-performance chip manufacturing with mature processes and advanced packaging, opening a door that had been almost closed for the domestic industry.

Kirin 2026: The Most Direct Mass Production Verification

The Changjiang Securities notes reported that Huawei's upcoming new machine will be equipped with the Kirin 2026 chip, the first flagship product designed entirely according to Tao's Law, and the most direct commercial verification of the aforementioned theory. Currently, Huawei has completed the wafer process for 381 chips designed according to Tao's Law.

Compared with the previous generation Kirin 9030, Kirin 2026's transistor density has increased from 1.55 billion per square millimeter to 2.38 billion per square millimeter, a 55% density increase. According to the traditional Moore's Law path, this range requires 3 years of geometric shrinkage and one complete process generation change to achieve.

Other key performance indicators: core energy efficiency increase by 41%, CPU frequency reaches 3.1GHz (an increase of 13%), and SRAM operating frequency improves by more than 40%.

Huawei has also revealed a long-term road map: The smartphone SoC frequency target is 3.39GHz by 2027, and 3.71GHz by 2028; by 2031, the transistor density target will reach 400 million per square millimeter, equivalent to 1.4nm process density level - and all this without relying on traditional process changes.

Investment Opportunities in Four Industry Chain Links

According to the research framework of Changjiang Securities, the implementation of Tao's Law will reshape the domestic semiconductor industry landscape along four main lines: