Intel EMIB-T vs. TSMC CoPoS: Yield Is the Real Threshold for Cost Advantage
Alina Collins
UBS's latest research frames Intel's EMIB-T and TSMC's CoPoS as coexisting market tiers, not a zero-sum fight — but whether either roadmap delivers hinges on yield and volume-production stability when both face the 2028 deadline.
How big is this market, and how do they split it?
UBS projects the advanced-packaging market will grow from $19 billion in 2026 to $122 billion by 2030 — a compound annual growth rate of roughly 59%.
Even if Intel captures 13%–18% share by 2030, TSMC could still hold 62%–67%. Both companies' revenues can grow simultaneously.
This means → the story is not about stealing share; it is about whether a rapidly expanding pie is large enough for two.
What problem do these two architectures actually solve?
Single dies are approaching reticle-size limits. Performance gains now depend on stitching multiple dies and more HBM — high-bandwidth memory — into one package.
EMIB-T — Intel's embedded multi-die interconnect bridge — takes the "patch the bridge locally" approach: it drops the large silicon interposer (a big slab of silicon acting as a highway between chips) and replaces it with small silicon bridges embedded in an organic substrate. Fewer process steps, lower theoretical cost, and easier scaling beyond 14× reticle sizes.
CoPoS — TSMC's chip-on-panel substrate — takes the "lay down an entire highway network" approach: it moves the redistribution-layer interposer from a round wafer to a rectangular panel, gaining advantages in interconnect density, signal integrity, 3D stacking, and future co-packaged optics.
In plain terms = one saves materials and steps for cost efficiency; the other uses a bigger base to push a higher ceiling. Different optimization targets, different ideal customers.
What is Intel's core contradiction?
EMIB-T theoretically eliminates the large silicon interposer and several process steps. But UBS field research shows its packaging yield sits at roughly 90%–92%, while high-value compute dies and HBM demand volume-production yields near the high-90% range.
The substrate is the harder problem: EMIB-T substrate yield is roughly 50%, standard EMIB substrate yield about 60%, and mature HPC ABF substrates exceed 80%. A single packaging failure scraps multiple expensive components at once.
This means → the interposer savings can be wiped out by bad substrates and scrapped dies — structural cost advantage does not equal finished-product cost advantage.
EMIB-T shifts more complexity onto the substrate. Substrate suppliers Ibiden and potential second source Unimicron benefit most directly; Ibiden has announced a ¥220 billion Gama factory investment, targeting volume ramp from late 2027 into 2028.
What is TSMC's core contradiction?
CoPoS's first generation will use a 310 × 310 mm panel, with volume production planned for 2028. A larger 510 × 515 mm panel follows.
Switching from round wafers to rectangular panels introduces new variables — warpage control, panel uniformity, equipment qualification, and yield ramp. Whether panel processes can replicate wafer-process stability is the key to delivering on time.
TSMC's moat lies in integrating leading-node fabrication, CoWoS, SoIC 3D stacking, testing, and future co-packaged optics under a single roadmap — offering "front-end plus back-end certainty in one package."
This reflects a bet not on any single packaging technology but on the irreplaceability of the entire chain.
Who delivers first in 2028, and what should we watch?
UBS expects EMIB-T to enter volume production in H2 2027 through 2028. The first major external project is likely Google's TPU v9, co-developed with MediaTek, with primary ramp in 2028.
CoPoS targets 2028 volume production. The first key customer is likely Nvidia's Feynman, with a window from H2 2028 into 2029, followed by AMD and other custom AI chips.
UBS notes that whether Google TPU v9 adopts EMIB-T on schedule and whether Nvidia Feynman lands on CoPoS are the real leading indicators — not current roadmap promises.
In plain terms = if either side delays, customers will default to whichever existing platform already has stable capacity. No one waits forever for a roadmap. Substrate yield and panel uniformity will determine whose technical promise converts into deliverable volume revenue.
Content is for reference only, not financial advice.