Intel Evaluates 14A2 Backside Power Delivery to Catch Up with TSMC
Taylor Wilson
Intel is evaluating dual-side power delivery for its next-gen 1.4 nm 14A2 node — a move that could shorten power paths and boost performance, but at the cost of sharply higher process complexity and yield pressure. This is the latest signal of a challenger trading technical risk for competitive leverage.
What exactly is dual-side power delivery?
Conventional chips deliver power from the front only. Backside power delivery — routing power lines beneath the chip — is already a cutting-edge approach. Dual-side means feeding power from both front and back simultaneously.
This means → shorter current paths, lower resistive loss, and chips that run faster on less energy.
In plain terms = a building with one elevator gets a second one at the back entrance — foot traffic (current) flows far more smoothly.
The trade-off is equally direct: process steps multiply, yield control becomes significantly harder, and the risk of defective chips rises.
Why is Intel taking this risk?
Intel already introduced GAA transistors — gate-all-around, a transistor design that wraps the gate around the channel for tighter current control — and PowerVia backside power delivery in its 18A node. Aggressive bets on new architecture are its established catch-up playbook.
This means → dual-side power at 14A2 is a natural extension: backside delivery is already in place, so adding front-side delivery is an "escalation," not a pivot.
This reflects Intel's core logic as a foundry-market challenger — differentiate on technology to win customer attention, because it cannot yet match TSMC on manufacturing stability.
What paths are Samsung and TSMC taking?
Samsung was the first to bring GAA into mass production at 3 nm. It plans to add backside power delivery in its enhanced 2 nm node SF2Z by 2027 — lower risk than Intel, because the backside layer sits on top of an already proven GAA architecture.
TSMC is the most conservative: GAA arrives only at 2 nm, and backside power delivery is expected to start at the A16 node. Its customer base and market share give it the leverage to prioritize production stability.
In plain terms = the leader locks in clients with mature technology; challengers create buzz with new technology. The three-way strategy split boils down to market position dictating technical boldness.
What is the central open question in this race?
Whether Intel's and Samsung's aggressive bets on ultra-advanced nodes can actually dislodge TSMC's dominance remains unanswered.
This means → no matter how advanced the roadmap, if yields fall short and customers do not commit, "paper leadership" cannot convert into orders.
Dual-side power delivery is still under evaluation; a final decision has not been made. For investors, the signal and direction matter now — not a delivery timeline.
Content is for reference only, not financial advice.