Jefferies: CPO-OIO Commercialization May Be Delayed Beyond 2030
Taylor Wilson
Jefferies' latest industry survey finds that CPO-OIO — the technology needed for direct GPU-to-GPU optical interconnect — may be delayed 2–3 years to 2030–2031 due to overheating on the interposer. This means → the timeline that once positioned OIO as the biggest driver of optical content growth in 2028 has visibly loosened, making pluggable optical modules the more bankable growth story for the next several years.
Why is OIO delayed?
OIO — Optical Input Output, a design that embeds optical engines directly onto the chip interposer — was championed by TSMC, targeting a 2028 launch via its COUPE platform.
Jefferies' field research found an overheating problem on the interposer, pushing the commercialization window from 2028 to 2030–2031.
In plain terms = OIO requires optical fiber, miniaturized FAU connectors, optical engines, high-power CW laser chips, and advanced packaging all to be ready at once. Any single bottleneck delays the whole chain — and right now the bottleneck is basic thermal management.
What went wrong with Nvidia's photonic chip?
Jefferies also disclosed that the photonic integrated circuit (PIC — a chip that moves data with light instead of electricity) used in Nvidia's Spectrum 6 switch chip has an electromigration issue.
The fix requires a respin with minor mask-layer adjustments, but does not affect its qualification timeline at TSMC.
This means → Spectrum 6's problem is a fixable engineering bug, not an architectural dead end.
With OIO delayed, what fills the gap?
Jefferies sees pluggable optical modules as the most bankable transition path through 2026–2029.
The upgrade trajectory is clear: 1.6T modules carry an ASP roughly double that of 800G and are just entering mass production this year; by 2028, modules may reach 3.2T with ASPs doubling again.
This means → the total addressable market for optical modules keeps expanding, pulling FAU (fiber array unit) and optical-chip demand — including EML, silicon photonics, and CW lasers — along with it.
What about cross-rack interconnect?
For cross-rack scale-out and scale-across workloads, migrating from pluggable modules to CPO is primarily driven by cutting power costs.
Jefferies judges this benefit less significant than the advantages OIO would unlock for intra-rack direct interconnect.
Integrating CPO onto the package substrate is technically less challenging, meaning cross-rack scale-up interconnect remains feasible over the next two years.
Where does chip-level innovation go instead?
With OIO on hold, Jefferies expects near-term chip-level innovation to center on two fronts: SoIC with stacked SRAM — TSMC's chip-stacking technology — and the A16 process node with its Super Power Rail.
Nvidia's next-generation Feynman GPU is now more likely to headline SoIC rather than OIO.
In plain terms = with OIO sidelined, chipmakers are channeling their energy into "stack chips higher, deliver power better" — the two paths that can ship on time.
Has Jefferies' long-term call changed?
No. Jefferies maintains that OIO remains one of the most important innovations for TSMC's long-term AI-chip sustainability.
The logic stands: die size cannot grow forever, and optical interconnect's advantages over copper — in data rate, heat, signal loss, and weight — do not disappear.
This reflects Jefferies' core view: optical content growth is delayed, not canceled — whether OIO lands on schedule after 2030 is the key test of that thesis.
Content is for reference only, not financial advice.