Kirin 9030 Teardown: SMIC N+3 Metal Pitch Beats Intel 18A, but Transistor Density Still Lags by 38%
Alina Collins
SMIC's N+3 process hits a 32.5 nm local metal pitch — narrower than Intel 18A's measured 36 nm — yet its transistor density reaches only 62% of Intel's. One narrow metric leads; the metric that matters lags, exposing the real limits of the DUV path.
Where does the "SMIC beats Intel" claim come from?
SemiAnalysis tore down the Kirin 9030 inside Huawei's Mate 80 Pro Max and found SMIC's N+3 local metal pitch at 32.5 nm — narrower than the 36 nm Intel 18A actually uses in Panther Lake.
This means → on that single metric, SMIC did etch finer lines, spawning online claims that "SMIC has surpassed Intel."
But Intel 18A supports a minimum pitch of 32 nm. Panther Lake uses the wider 36 nm because it introduced PowerVia — a backside power delivery technology that moves power wiring behind the wafer, freeing the front-side metal layers for signal routing.
In plain terms = Intel chose wider pitch, not because it couldn't go narrower, but because moving power to the back gave it roughly 10% higher density overall.
How large is the transistor-density gap?
Metal pitch captures only local line-etching ability. Transistor density is the core benchmark — it directly determines performance and power efficiency.
SemiAnalysis measured SMIC N+3 at 113.4 million transistors per mm², barely above TSMC's mature N6 node and 38% behind Intel 18A.
Side by side: Intel 18A ≈ 238 M/mm², TSMC N3P ≈ 224 M, Samsung SF3 ≈ 190 M. TSMC's N2, entering mass production this year, reaches 313 M — roughly 2.5× SMIC N+3.
This reflects what TechInsights analyst Rajesh Krishnamurthy noted: N+3 is essentially an extension of SMIC's earlier 7 nm work, sitting at the 6 nm tier — behind TSMC's and Samsung's 5 nm.
Without EUV, what is SMIC's workaround?
U.S. export controls block SMIC from obtaining EUV lithography tools — the extreme-ultraviolet machines that are standard equipment for today's leading-edge nodes.
The alternative: DUV lithography — deep-ultraviolet light, one generation older — combined with multi-patterning, up to quadruple exposure. Each circuit layer is etched in four passes to achieve finer lines.
N+3 also stacks density-boosting techniques: dual-fin transistors, contact-over-active-gate (COAG), and single diffusion break (SDB) — nearly exhausting every optimization available on current equipment.
This means → the cost is more masks, more etch steps, longer cycle times. Wafer cost and manufacturing complexity rise in lockstep — engineering ingenuity has reached its edge, and so has the cost ceiling.
Where does Kirin 9030 performance actually land?
Compared with Huawei's previous generation, the Kirin 9030 shows clear gains: CPU core count rises to 12–14, Huawei claims GPU performance up to 79% higher, and hardware ray tracing debuts — though none of these claims have been independently verified.
SemiAnalysis offers a cooler cross-industry read: the peak core runs at 2.75 GHz, with single-core performance close to Arm's Cortex-X2, released in 2021.
In plain terms = overall performance roughly matches Android flagships from three years ago. The top CPU core trails Apple's 2020 M1 by 57%; GPU performance lags Qualcomm's and MediaTek's latest flagships by 2.4–3.2×.
How far can this technology path go?
The Kirin 9030 proves SMIC can still advance its process under severe equipment restrictions — an engineering achievement in its own right.
But three dimensions together define the ceiling: density stuck at the 6 nm tier, performance trailing global flagships by three years, and DUV multi-patterning costs still compounding.
This reflects the distance between "leading on one narrow metric" and "leading on overall process" — etching one finer line does not make the whole chip more advanced.
This means → the next test is no longer "can you etch finer" but whether density, performance, and cost can break through simultaneously.
Content is for reference only, not financial advice.