Nomura: Major Boost for Google's 8th Generation TPU Supply Chain, Shipment Expectations up to 10 Times
Miles Bennett
Google is splitting its training and inference chips into two dedicated TPUs for the first time; Nomura expects the move to drive shipments to 10x the prior generation, pulling up optics, copper, PCB, and the entire supply chain.
Why split one chip into two?
Training and inference workloads have diverged sharply: training needs massive clusters syncing giant models; inference needs low latency, high concurrency, and long context windows.
This means → a single chip trying to serve both is increasingly a compromise.
Google's answer: TPU 8t handles training, TPU 8i handles inference — separate architectures, separate networks, separate design partners.
What does each chip bring to the table?
TPU 8t (training): single-Pod scale at 9,600 chips, per-chip bidirectional bandwidth of 19.2 Tb/s (2× the prior gen), cost-performance up to 2.7× better.
TPU 8i (inference): dual-die design, 288 GB HBM, 384 MB on-chip SRAM (3× that of 8t) — resources concentrated on memory and low latency.
In plain terms = 8t is built to compute more; 8i is built to answer faster.
Where does the supply-chain money flow?
OCS — optical circuit switches: Google has introduced OCS into 8i's inter-group interconnect, a structural change. The key question is whether OCS can move from small batches to volume production.
1.6T optics and NPO/CPO: optical lane rate is now 400G, pushing bandwidth pressure higher. Pluggable 1.6T modules remain the near-term mainstream, but co-packaged optics closer to the chip are gaining strategic importance.
Copper: 8i still relies heavily on copper within groups — up to 3,168 DAC cables per Pod. This reflects that short-reach, high-reliability connections still depend on copper, connectors, and cable assemblies.
Why is the CPU suddenly important again?
AI is shifting from single-turn Q&A to agentic workloads — calling tools, reading and writing databases, running code — all of which lean on CPUs.
Google is deploying its in-house Arm-based Axion CPU as the host processor for the first time; the CPU-to-TPU ratio moves from 1:4 to 1:2, doubling CPU count per server.
Intel's CEO notes the ratio has already moved from 1:8 to 4:1, and may approach 1:1. Arm CEO Rene Haas projects data-center CPU capacity could grow over 4×, with the market exceeding $100 billion by 2030.
Who is building these two chips for Google?
Google maintains a dual-vendor strategy: 8t is co-designed with Broadcom; 8i is co-designed with MediaTek — a first for MediaTek in Google's TPU program.
PCB, copper-clad laminates, substrates, server assembly, and ASIC design services all stand to benefit. Nomura specifically names Shenghong Tech among substrate and PCB suppliers.
This means → the 10× shipment increase is not just a chip story — it is a system-wide volume ramp from optics to copper, from boards to enclosures.
Content is for reference only, not financial advice.