Samsung Develops Glass Interposer as TSMC Expands Chiayi Packaging Facility to Four Fabs
N.R. Finch
Samsung Electronics and Samsung Display are co-developing a glass interposer prototype due by year-end for pitch to global tech firms; meanwhile TSMC's Chiayi packaging campus has grown to four factories, sharpening the advanced-packaging race between the two giants.
What is a glass interposer, and why replace silicon?
An interposer — the middle layer between a chip die and its package substrate, routing electrical signals from one to the other — is currently made almost exclusively from silicon.
Glass offers three advantages: a flatter surface → finer wiring; a lower thermal expansion coefficient → less warping when chip and substrate heat up at different rates; and panel-scale processing → potential to cut reliance on costly silicon wafers.
In plain terms = a silicon interposer etches circuits on a small, expensive silicon wafer; a glass interposer does the same job on a larger, flatter, cheaper glass sheet — potentially higher precision at lower cost.
What role does Samsung Display play?
Samsung Display has set up a dedicated R&D team to build redistribution layers (RDL) — fine-pitch wiring that re-routes chip signals to the correct connection points — directly on glass.
AI-processor interposers may require dozens of uniform RDL layers, demanding metal deposition, lithography, etching, and plating — processes that overlap heavily with Samsung Display's existing expertise in forming fine circuits on large glass panels.
This means → Samsung is not making an experimental leap; it is redeploying proven display-panel manufacturing skills into the semiconductor-packaging arena.
What is the biggest technical hurdle right now?
Samsung Display faces a delamination defect called "SeWaRe": after an insulating film is coated onto glass and diced into units, the thermal-expansion mismatch between glass and the organic material creates stress that can cause layer separation or glass tearing.
In plain terms = the two materials expand at different rates when heated; bonded together, they tend to pull apart — until this is solved, yield stays low.
Samsung Display is working with material suppliers to fix the problem; Samsung Electronics, meanwhile, has outsourced TGV (through-glass via) formation, copper filling, and related steps to Korean firms Soulbrain, Chemtronics, and JWMT.
What is TSMC doing on its side?
TSMC is adding a third and fourth advanced-packaging fab at its Chiayi Science Park campus; the first is already in volume production, and the second is about to follow, Reuters reported.
This means → TSMC's CoWoS — Chip-on-Wafer-on-Substrate, the dominant packaging platform for AI processors — capacity is scaling fast, tracking demand from Nvidia and other AI-chip designers that continues to outstrip supply.
This reflects a broader shift: advanced packaging is no longer a back-end afterthought — it is one of the tightest capacity bottlenecks in the AI compute race.
Does Samsung have a second glass initiative?
Samsung Electro-Mechanics is developing glass-core substrates — a different product from the glass interposer: the substrate is the bottom-most carrier board in a package, while the interposer sits between the die and the substrate.
Samsung Electro-Mechanics signed a JV agreement with Dongwoo Fine-Chem (a wholly owned subsidiary of Sumitomo Chemical) on July 2; the JV is expected to launch in 2026, with a supply chain in place by H2 2027.
In plain terms = Samsung's broader group is pursuing "glass replaces silicon" on two parallel tracks — one for the middle layer (interposer), one for the bottom board (substrate).
What is the key milestone to watch?
Whether Samsung's glass-interposer prototype reaches a presentable state by year-end is the first checkpoint.
The harder test comes after: can yield and reliability meet the stringent requirements of AI processors — the dividing line between a lab result and a production-ready solution.
This means → Samsung's integrated strategy — foundry plus packaging under one roof — cannot credibly challenge TSMC's CoWoS / CoPoS ecosystem until this prototype clears. The earliest verdict arrives in late 2025.
Content is for reference only, not financial advice.