Samsung Electronics Unveils High Bandwidth Memory HBM5 for the First Time
N.R. Finch
Samsung publicly demonstrated its 8th-generation high-bandwidth memory, HBM5, at Computex 2026 in Taipei — just five months after shipping HBM4; the pace signals an aggressive push to shift from market follower to narrative leader in AI memory.
What is HBM5, and why show it now?
HBM5 is the 8th generation of high-bandwidth memory — ultra-fast memory designed specifically for AI chips. Samsung showed a physical unit at Computex 2026.
The timeline is the story: HBM4 only began mass production in February this year. Five months later, the next generation is already on display. This means → Samsung is deliberately compressing its product cadence, racing to define the technology direction before rivals can.
HBM5 maps to Nvidia's next-generation GPU architecture, "Feynman," which the market expects to enter mass production in 2028–2029. In plain terms = Samsung is showing a chip that won't ship for two to three years. The goal isn't sales — it's staking a claim.
How does it improve on HBM4?
The core memory stack stays on 1c DRAM (6th-gen, 10 nm-class), but the base die — the "foundation" of the entire stack — upgrades to Samsung Foundry's 2 nm process. That is the key technical difference from HBM4.
Projected specs show a clear leap: per-stack bandwidth of 4 TB/s, I/O width expanded to 4,096 bits, and maximum per-stack capacity of 80 GB.
This means → compared with HBM4's 3.3 TB/s, HBM5 bandwidth rises roughly 21%, while the capacity ceiling climbs sharply. AI models keep getting larger; memory must keep up.
Where does Samsung actually stand in the market?
The reality is stark: in Q2 2025, SK Hynix held roughly 62% of global HBM market share; Samsung held about 17%.
Yield problems during the HBM3E cycle cost Samsung key Nvidia orders. Customer trust only began to rebuild this year after HBM4 samples passed qualification at Nvidia, Broadcom, and AMD.
Samsung expects its HBM revenue this year to exceed three times the 2025 figure. This reflects a real revenue recovery from the HBM4 customer wins — but the share gap with SK Hynix remains enormous.
Hybrid bonding — what is the make-or-break variable?
Hybrid bonding — a process that joins two chips directly, copper pad to copper pad — is the core uncertainty for HBM5's on-schedule delivery.
The theoretical performance advantage is clear, but the process demands extreme manufacturing precision, and yield ramp carries significant uncertainty. In plain terms = making it work in a lab and making it work at factory scale are two different things.
This means → if Samsung can crack yields between the HBM4E and HBM5 generations, it can re-establish a competitive edge in high-end stacks of 20+ layers. If it cannot, the gap with SK Hynix could widen again.
What comes next on Samsung's roadmap?
Beyond HBM5 sits the 9th generation, HBM5E, whose core stack is planned to upgrade to 1d DRAM (7th-gen, 10 nm-class). It remains in internal R&D.
At Computex, Nvidia CEO Jensen Huang was also in Taipei. The market is watching for further signals on next-generation memory collaboration between the two companies.
This reflects a deeper shift: the AI memory race is no longer just about "who ships first" — it is about who locks in the downstream GPU platform's technology roadmap. By unveiling HBM5 early, Samsung is effectively signaling to Nvidia and the wider market: our cadence can keep up.
Content is for reference only, not financial advice.