Samsung Slows 1d DRAM and 10th-Gen NAND Investment as High Margins on Existing Lines Reduce Urgency for Node Transition
Miles Bennett
Samsung is delaying investment in 1d DRAM and 10th-generation NAND because surging memory prices already make current production lines highly profitable — rushing to unproven next-gen nodes would squeeze margins, not expand them. The whole memory industry is shifting from chasing new nodes to milking existing ones.
Why is Samsung in no hurry to move to 1d DRAM?
1d DRAM — the seventh-generation 10nm-class node — is funded at pilot-line level only, with the earliest ramp-up slated for late 2026 to early 2027.
Key production equipment is still in development; suppliers target delivery by Q2 2027, pushing realistic initial mass production to late 2027 at the earliest.
This means → at least 18 months separate pilot from volume. Samsung is not racing.
A person familiar with Samsung's operations put it bluntly: node transitions historically happen during downturns, but memory prices are extremely high right now — existing lines generate ample profit, so the urgency to switch has dropped sharply.
1c DRAM is locked in for HBM5 — what does that mean for 1d?
Samsung will use 1c DRAM — the sixth-generation 10nm-class node — in its HBM5 products. It began sampling 12-layer HBM4E to key customers in late May.
In plain terms = 1c is both the current volume workhorse and the foundation for near-term premium products. There is no reason to retire it while it still prints money.
This means → 1d DRAM has shifted from "next stop" to "the stop after next," its timeline stretched by 1c's extended lifecycle.
Why is 10th-gen NAND even harder to push forward?
Investment in 10th-gen NAND has been postponed multiple times since the second half of last year. The core obstacle: the process itself gets more expensive.
Starting with the 10th generation, Samsung plans to adopt wafer bonding — fabricating storage-cell arrays and peripheral circuits on two separate wafers, then joining them. Each finished chip consumes two wafers plus extra manufacturing steps, pushing unit costs significantly higher.
In plain terms = one wafer used to yield one chip; going forward it takes two — a near-doubling of input cost.
Samsung's 9th-gen NAND already achieves 286 layers on a single wafer, leading rivals without bearing the extra cost of wafer bonding. With that advantage still intact, the incentive to absorb higher costs shrinks further.
Rivals already use wafer bonding — why can Samsung still wait?
YMTC (Xtacking brand) and Kioxia (CBA architecture) have both commercialized wafer-bonding technology.
But Samsung's 9th-gen NAND leads on layer count within a single-wafer architecture. This means → it does not yet need to switch to a costlier process just to keep up on layers.
An equipment-industry source was explicit: investment priority clearly favors DRAM over NAND right now.
Is it just Samsung — or is the whole industry milking existing capacity?
SK Hynix faces similar constraints. Limited cleanroom capacity means near-term capex will likely concentrate on expanding 1c DRAM output to support its HBM4E program.
Apple CEO Tim Cook said in the company's January earnings call that Apple faces significant memory-price inflation.
This reflects the AI infrastructure boom steering capacity toward high-bandwidth memory and tightening conventional chip supply. Samsung has signaled that capacity expansion in 2026 and 2027 will remain restrained.
Where does this strategy hit its limits?
The logic is clear: when the price cycle is strong enough, the switching cost of a next-gen node becomes a burden. Makers prefer to maximize output on mature nodes with proven yields.
In plain terms = make money while you can; save the new tech for after prices fall.
But this strategy has a time window — whether 1d DRAM mass production materializes by late 2027 will be the key test of when the "milk the old node" logic peaks.
Content is for reference only, not financial advice.