Samsung to Open 2nm MPW Services Next Year, Boosting Korea's Chip Design Ecosystem
N.R. Finch
Samsung Foundry disclosed its first-ever 2nm MPW schedule — seven shuttle runs next year — lowering the barrier to cutting-edge process development from 4nm straight to 2nm. This means → smaller Korean chip designers can now test-drive the most advanced node without bankrolling an entire wafer.
What is MPW, and why does the jump to 2nm matter?
MPW — multi-project wafer, combining several companies' chip designs on a single wafer for prototype runs — lets small firms skip the cost of a full wafer to trial advanced nodes.
Samsung's MPW ceiling was 4nm; next year it leaps to 2nm. This means → the development barrier drops two full generations in one step, opening the frontier to teams that could never afford it alone.
In plain terms = testing a 2nm design used to require booking an entire wafer at enormous cost. Now companies can share one, slashing the price tag.
How packed is the shuttle schedule?
Samsung will run 7 MPW shuttles each for 2nm and 4nm, plus 11 runs spanning 5nm to 28nm — 18 in total. Including legacy 8-inch nodes, the count rises further.
This means → Samsung is laying down a dense calendar so design houses have year-round windows to tape out, rather than waiting for one or two slots.
This reflects the foundry division's strategic priority: thicken the ecosystem first with MPW, then convert participants into volume-production customers.
Where does 2nm mass production actually stand?
Foundry executive Song Tae-jung said Samsung's first-generation 2nm process, SF2, is progressing toward mass production, targeting HPC, AI, and automotive chips.
He stressed that Samsung was the world's first to mass-produce 3nm GAA — gate-all-around, a transistor architecture that wraps the "switch" on all four sides instead of three, giving tighter current control and lower power.
In plain terms = the 3nm GAA track record is Samsung's credential; 2nm is the next step — but on-time delivery and yield remain the market's open questions.
How does Samsung help designers go from blueprint to production?
Through the SAFE partner network — spanning design-IP vendors, EDA (electronic design automation — the specialist software used to draw chip circuits) firms, and design-service houses — Samsung offers fabless companies end-to-end support from design through verification to volume production.
In defense, Samsung formed the K-on-device consortium with Korea Aerospace Industries (KAI) to develop and produce military-grade semiconductors.
This reflects a broader ambition: Samsung wants to be not just a capacity seller but the infrastructure layer of Korea's chip-design ecosystem, closing the loop among demand-side players, designers, and suppliers.
What does this mean for the market?
Whether 2nm MPW launches on schedule — and attracts enough design customers — is the key test of Samsung Foundry's ecosystem competitiveness.
This means → for Samsung, proving the technology works at 2nm is only half the exam; the other half is whether anyone shows up to use it.
About 150 attendees joined the M.AX Alliance conference, representing chip-demand firms, fabless houses, IP companies, and the Korea Semiconductor Industry Association; a semiconductor manufacturing-support working-group agreement was signed — Samsung is actively widening its circle.
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