Samsung's Jay Y. Lee Visits AI Chip Packaging Lab in Japan
nashnova research
Samsung chairman Lee Jae-yong visited the company's Advanced Packaging Laboratory in Yokohama on November 1. Samsung plans to invest ¥40 billion over five years to bolster AI chip packaging — a move that signals Samsung is grafting Japan's materials edge onto its own packaging weak spot to challenge TSMC on AI's next battleground.
What does this lab actually do?
The APL sits in Yokohama, Japan. Set up in 2023, it focuses on developing and evaluating advanced packaging materials and processes — in plain terms, figuring out how to bundle multiple chips together more tightly and efficiently.
Over 50 Japanese companies — including Tokyo Electron and Ibiden — are research partners. Nearly 100 Japanese and Korean engineers are already on site.
This means → Samsung placed the lab in Japan not for show, but to plug directly into Japan's materials and equipment supply chain, the world's primary source of packaging raw materials.
Why build the lab in Japan instead of Korea?
The core reason is speed. Shipping Japanese materials to Korean R&D facilities used to take roughly two months round-trip. On-site testing should compress that cycle sharply, though Samsung has not disclosed by how much.
In plain terms = R&D is an iteration race. Two extra months in transit means two months' delay to market. Moving the lab next to the materials trades distance for time.
Japan's central government will provide up to ¥20 billion in subsidies; Yokohama city adds another ¥2.5 billion, with national funds expected by 2028. This reflects Japan's own interest in pulling its materials industry into the AI chip race via Samsung.
Where does Samsung's AI chip business stand now?
Three days before visiting the APL, Lee attended Samsung's earnings call. Key numbers: HBM4 sales more than tripled quarter-on-quarter, accounting for roughly 60% of total HBM revenue in Q3.
HBM4 — the fourth generation of high-bandwidth memory — entered mass production in February. It pairs sixth-generation 1c DRAM with a logic base die built on Samsung's 4 nm process. This means → Samsung is already using its own foundry line to make the "base" for its own memory. The memory and foundry tracks are merging.
On the foundry side, 2 nm HPC orders from major hyperscale cloud providers are also driving revenue growth.
What is Samsung's bigger play?
The Yokohama investment is one piece of Samsung's push to integrate memory, foundry, and packaging. The goal: offer AI customers a single source for chip design, memory, manufacturing, and packaging.
In plain terms = today, an AI chip customer must separately source design, memory, foundry, and packaging — a complex, inefficient process. Samsung wants to collapse those four steps into one, with a single point of contact.
The APL's research scope may expand to wafer bonding — joining two wafers face-to-face — and glass substrates — using glass instead of traditional organic material as the chip's base — among other next-generation packaging architectures.
Can Samsung catch TSMC?
TSMC disclosed in April 2026 that it is producing 5.5× reticle-size CoWoS packages — a technology that places multiple chips and memory side by side — and plans a 14× reticle-size platform by 2028, capable of integrating roughly 10 large compute dies and 20 HBM stacks.
TSMC has also operated a 3DIC research center in Tsukuba, Japan since 2022, working with Japanese partners on next-generation packaging. This means → Samsung's Japan lab strategy is not unique; TSMC got there at least a year earlier.
Samsung has not yet disclosed any commercial product tied to APL research, nor a timeline for production. This reflects the central open question: whether Japanese materials research can translate into production-ready packaging competitiveness — the key test of whether Samsung can close the gap with TSMC.
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