SanDisk Patent Revealed: Processor, Flash Memory, and HBM Integrated into a Single Chip
Miles Bennett
SanDisk has published a US patent proposing to stack a multi-core processor directly on top of a NAND flash tile and integrate HBM on the same interposer — an architecture aimed at cracking both the capacity and speed bottlenecks of AI compute.
What exactly does this patent propose?
The core idea: place a GPU or AI accelerator directly on top of a CBA storage tile — a single unit bonding a CMOS logic die to a NAND flash array — then mount HBM memory stacks around the edges, all on one interposer (a silicon "bridge board" that connects different chips).
This means → the physical distance between compute and storage shrinks dramatically, cutting the data-travel path and lowering power draw.
In plain terms = data used to take a long detour to reach the processor; SanDisk wants storage sitting right underneath it.
The patent, numbered US 12,430,274 B2, was filed with the USPTO and first reported by tech outlet Wccftech.
Why isn't HBM enough anymore?
Today's mainstream HBM — high-bandwidth memory, DRAM layers stacked vertically with through-silicon vias — tops out at roughly 32–64 GB per stack. Extremely fast, but limited in capacity.
This means → as AI model parameters keep growing, HBM hits a ceiling — not a speed problem, but a size problem.
SanDisk previously introduced HBF (High-Bandwidth Flash), borrowing HBM's stacking approach but using NAND flash via TSVs. Target capacity: several terabytes, roughly 8–16× HBM at comparable bandwidth and cost.
But NAND's physics means its access speed still trails DRAM — and that gap is exactly what the new patent aims to close.
What does this patent add beyond HBF?
HBF solved "not enough room" — swap in flash for some DRAM and expand the memory pool.
The new patent tackles "too far away" — via 3D stacking, the NAND flash tile sits directly beneath the compute chip instead of connecting remotely across a motherboard.
In this architecture, HBM handles instant, high-speed reads and writes (like sticky notes on your desk), while the NAND flash layer takes on bulk data storage and write-heavy workloads (like a filing cabinet within arm's reach).
This reflects a shift in SanDisk's roadmap: from "make bigger storage" to "give storage a defined role inside the compute hierarchy."
Where does SanDisk's product timeline stand?
SanDisk plans to deliver first HBF samples in H2 2026, with the first AI inference devices carrying HBF expected in early 2027.
The company has signed a partnership with SK Hynix and is advancing HBF spec development under the Open Compute Project (OCP) framework.
This means → HBF is already in the engineering-delivery phase, while the "processor + flash + HBM on one interposer" design in this patent is a further-out technology reserve — not yet on a product roadmap.
What is the broader industry pushing toward?
Samsung and SK Hynix have warned that AI-driven memory supply tightness could persist through 2027 or longer.
This means → the "memory wall" — processors fast enough but starved of data — is becoming the central bottleneck in AI compute scaling, not a side issue.
SanDisk's patent intent is to push NAND out of its traditional "cold storage" role and into a memory tier closer to the compute core — a path that complements rather than replaces Samsung's and SK Hynix's HBM expansion.
How far is this patent from a real product?
A published patent is not a product roadmap — engineering execution, industry standardization, and downstream customer adoption all stand between paper design and mass production.
In plain terms = this is closer to SanDisk "staking a claim" — locking in a technology direction first; whether and when it ships is a separate question.
For investors, the key watch window is HBF sample delivery in H2 2026 — that is the first hard milestone testing whether SanDisk's "storage next to compute" thesis can actually work.
Content is for reference only, not financial advice.