SemiAnalysis: SMIC 7nm and CXMT Memory Found in Huawei Kirin 9030
Taylor Wilson
Chip-analysis firm SemiAnalysis tore down Huawei's Kirin 9030 and found SMIC's third-generation 7 nm-class process alongside CXMT's LPDDR5X in one flagship SoC — the first time domestic advanced logic and mobile DRAM have shipped together in a high-end handset, marking a tangible step for China's semiconductor supply chain into the premium tier.
How dense is SMIC N+3, really?
Teardown measurements show N+3's minimum metal pitch (M0) at 32.5 nm — below the 36 nm found in Intel's 18A Panther Lake product.
Transistor density reaches roughly 113.4 million per mm², slightly above TSMC N6's approximately 107.7 million per mm². Standard-cell height is about 228 nm, down roughly 9.5% from N+2's 252 nm.
This means → Kirin 9030's CPU cores shrank by about 20%, freeing room to pack more CPU, GPU and NPU cores plus extra cache into nearly the same die area.
In plain terms = SMIC does not have the most advanced lithography tools, yet the circuit density it achieved sits close to TSMC's previous-generation workhorse node.
Without EUV, how did SMIC push density this far?
To hit 32.5 nm pitch, SMIC used SAQP — self-aligned quadruple patterning, meaning the DUV scanner exposes the same layer four times to reach the target resolution. Some upper metal layers use SADP (double patterning).
In plain terms = TSMC has EUV and can print the pattern in one shot. SMIC doesn't, so it repeats the same step multiple times to approximate the same precision — at the cost of more masks, tighter overlay control and higher expense.
This reflects a clear strategy: aggressive DUV multi-patterning + DTCO (design-technology co-optimization) + compact standard-cell design, pushing density into the TSMC-N6 neighborhood.
But this route cannot fully replicate the EUV path on cost, performance or power efficiency. What it proves is that export controls have not frozen China's advanced logic progress — not that the gap has closed.
How did CXMT land inside a flagship phone?
The 12 GB Kirin 9030 Pro uses Samsung LPDDR5X. The 16 GB Pro Max sample, however, contained both Samsung and CXMT memory packages.
The CXMT package is marked CXDD7JEDM, dated to week 45 of 2025, housing two groups of four-high stacks — eight DRAM dies in total.
X-ray CT scans suggest the die size is consistent with CXMT's G4 process at roughly 0.3 Gb/mm², broadly equivalent to the international 1z-class DRAM node.
This means → CXMT can ship alongside Samsung in the same handset model, which signals it has cleared the critical thresholds in capacity, power, stability, yield and supply-chain qualification. Entering a flagship phone is a harder proof of maturity than a product announcement alone.
Does one leading teardown metric prove overall process leadership?
No. M0 pitch is one dimension among many. Transistor architecture, the full interconnect stack, routability, metal and via resistance, design rules, mask count, yield and real-world performance-per-watt are all necessary to judge a process node holistically.
A clear gap remains between SMIC N+3 / CXMT G4 and the global cutting edge — one standout metric does not erase that.
This reflects the question that actually matters going forward: whether China's domestic semiconductor chain can keep delivering along the path of stable manufacturing → flagship-product adoption → scaled supply — that trajectory, not any single parameter, is the real verification point to watch.
Content is for reference only, not financial advice.