Taiwan Industry Questions Korean Media Report: TSMC's PLP Mass Production Timeline Called Overly Aggressive
Claire Weston
Korean media claims TSMC could begin panel-level packaging (PLP) mass production as early as 2027. Taiwan industry sources counter that TSMC's own guidance — R&D readiness by 2027, commercialization after 2028 — has not changed.
What did the Korean report claim, and why does Taiwan disagree?
Korea's ETNews reported on June 15 that TSMC is building a PLP (panel-level packaging) supply chain, with mass production potentially starting in 2027, and has already secured a global AI chip client.
Taiwan's *Economic Daily News* cited industry sources in response: TSMC's latest public guidance puts fan-out panel-level packaging (FOPLP) at R&D readiness by 2027, with larger-scale commercialization after 2028 — no change.
This means → the Korean report equated "R&D ready" with "mass production." Taiwan's industry sees at least a one-year gap between the two.
What has TSMC itself said?
Chairman C.C. Wei stated at a July 2024 investor meeting that FOPLP is not yet mature and needs at least three more years to be ready. TSMC would continue development as a contingency.
On CoPoS — Chip-on-Panel-on-Substrate, a next-generation method that mounts chips on a panel and then onto a substrate — Wei recently disclosed that a pilot line is up, but mass production is still two to three years away.
In plain terms = TSMC's own pace is "prove it in R&D first, then scale." No steps are being skipped.
Why does PLP matter?
PLP (panel-level packaging) replaces the traditional round wafer with a rectangular panel, eliminating wasted space at the wafer's curved edges.
A single 600 × 600 mm panel yields roughly five to six times the output of a standard 300 mm wafer.
This means → output per unit area jumps significantly, promising lower packaging costs — the scarcest efficiency lever in the era of large AI chips.
Is Samsung already ahead?
Samsung Electronics acquired PLP operations from Samsung Electro-Mechanics in 2019 and is widely regarded as having the most experience in the field.
The technology is already used in mobile application processors and power-management chips. Samsung plans to extend it to high-performance computing and AI semiconductors.
Glass substrates are also seen as a potential PLP material. This reflects a brewing head-to-head competition between Samsung and TSMC in next-generation substrates.
Who is moving first across the supply chain?
Outsourced assembly and test firms (OSATs) are expected to lead FOPLP adoption, while TSMC focuses on higher-end next-generation CoWoS and CoPoS development.
Equipment progress is already tangible: Manz Asia announced on June 15 that it delivered what it calls the world's first 310 × 310 mm PLP electrochemical deposition production system, supporting FOPLP, CoPoS, and through-glass-via architectures.
In plain terms = OSATs pave the road, TSMC takes the high end, and equipment makers are already shipping — the division of labor is forming, but TSMC's own volume ramp remains the key variable.
Content is for reference only, not financial advice.