TSMC 3nm Lead Time Exceeds One Year as IC Design Houses Scramble for Packaging Capacity
Miles Bennett
TSMC's 3nm lead times have stretched past one year while packaging and testing capacity tightens in parallel — IC design firms now face a two-front squeeze that signals a systemic supply-chain shock from surging AI chip demand.
How long is the 3nm queue?
Nvidia, Apple, AMD, Broadcom, and Marvell have locked up large blocks of advanced-node capacity, pushing TSMC's 3nm lead time past one year for new orders.
This means → an IC design firm placing an order today will not see finished chips until mid-2027 at the earliest. The window is extremely crowded.
Tech giants are accelerating "multi-foundry" strategies. In plain terms = they are spreading bets across Samsung and Intel instead of relying on TSMC alone.
Why are packaging and testing prices rising too?
IC design firms in Taiwan, Europe, and the U.S. all report that packaging, testing, and related materials have entered a broad supply constraint — advanced and legacy packaging are equally tight.
Taiwanese IC design houses note the sector had seen no significant price adjustments for years; the sharp increases in H2 2025 are a clear warning signal from the market.
This means → designing a chip is only step one; "putting it in its package" is just as bottlenecked — and prices have room to climb further until new packaging lines come online.
How are IC designers fighting for capacity?
Entering H1 2026, companies are prioritizing products with stronger order visibility or where customers have pulled in shipments, while broadening their supplier pools.
A geographic split is emerging: products for the China market go first to mainland Chinese OSAT houses; products for other markets lean on Taiwan or Southeast Asian suppliers.
Western firms are willing to pay a premium to lock in resources. Suppliers allocate quotas through pricing when capacity is limited — this reflects a dynamic where downstream customers are effectively trading higher cost for delivery certainty.
Where does the pressure fall hardest on Taiwanese IC designers?
Western firms' willingness to pay up directly raises cost-structure pressure on Taiwanese IC design houses — the same packaging slots now cost more to retain.
In plain terms = the "default share" Taiwanese firms held through geographic proximity is now being pried loose by Western rivals with hard cash.
IC design companies expect the battle for packaging capacity over the next two years to be fiercer than anything in recent memory — capacity directly caps shipment volume and revenue growth.
Samsung vs. Intel — who takes the No. 2 foundry spot?
Samsung has secured the production contract for Tesla's next-generation autonomous-driving chip AI6, and is in discussions or collaboration with Nvidia, Google, Groq, and AMD.
Notably, Samsung is positioned to win the I/O die for Google's next-gen TPU10 "Icefish" — the component linking HBM (high-bandwidth memory) to the processor — which would showcase Samsung's integrated HBM-plus-advanced-packaging capability.
Intel, however, is competing hard for the same No. 2 position; Samsung's Taylor, Texas fab and Intel's U.S. facilities are expected to chase the same pool of customers. This means → TSMC's capacity bottleneck has not automatically funneled orders to Samsung — instead, it has turned into a credibility contest between Samsung and Intel over who can deliver superior technology and capacity.
What is Samsung's make-or-break milestone?
Samsung's foundry division has accumulated losses of several trillion won and lists a return to profitability as its top priority, targeting 2028.
In plain terms = Samsung Foundry has been burning cash to acquire customers; it now must prove the Tesla contract can trigger a chain reaction — attracting more tech-giant orders.
Whether Samsung can parlay the Tesla win into broader adoption while keeping the Taylor fab running smoothly will determine if its foundry business stays in the red or genuinely turns the corner.
Content is for reference only, not financial advice.