TSMC: AI Advanced Packaging Competition Extends to System-Level Reliability
Nashnova编辑部
TSMC's advanced-packaging VP Kevin He told the 2026 OCP Asia-Pacific Summit that AI packaging competition now stretches from single-die performance to rack-level reliability — this means → every layer of the machine must be audited for defects, not just individual components.
How much does SoIC outperform CoWoS — and why does it matter?
TSMC's SoIC — a 3D packaging technology that stacks chips vertically — delivers 56× the interconnect density of CoWoS (a 2.5D side-by-side approach) and 5× better power efficiency.
This means → the "data highway" between chips is 56 times denser and five times more power-efficient. The AI bottleneck is shifting from raw compute speed to data-transfer bandwidth and energy cost.
Pitch roadmap: 9 µm in 2023 → 6 µm in 2025 (now in mass production) → 4.5 µm targeted for 2029, matching the A14 process node at each step.
In plain terms = smaller pitch means more chip-to-chip connections per unit area, which means faster data movement. TSMC plans to double that density again over six years.
Why is "pass at the component level" no longer enough?
He proposed breaking AI system reliability into four tiers: rack → tray → board → component, with a whole-rack defect target below 1,000 DPPM (defective parts per million).
The math cascades down: 20 trays per rack → tray target below 50 DPPM; two boards per tray → board target below 25; two components per board → component target below 12.
This means → the component-level bar drops to 12 DPPM — far stricter than consumer electronics, forcing TSMC and its customers to shift from "part-level pass" to "whole-machine pass."
What does each tier require?
Rack tier: beyond redundancy and fault tolerance, stronger thermal management and co-designed hardware-software verification.
Tray tier: design for manufacturability (DFM — making designs inherently suited to mass production), design for assembly (DFA — reducing assembly errors), plus module-level stress and burn-in testing.
Board tier: reliability design such as ECC (automatic error correction), wafer-level aging tests including HTS (high-temperature storage) and HTOL (high-temperature operating life) accelerated stress tests.
Component tier: TSMC-led wafer-level CP testing, die-level testing, reliability screening, and redundancy design.
What new risk does the glass-cloth shortage create?
Surging AI demand has caused a global shortage of glass cloth — the core substrate material for CoWoS packaging. TSMC had to expand from a single source to more than five suppliers.
Diversification alone does not lower risk: glass cloth from different suppliers varies in thermal expansion coefficient and elastic modulus, which can affect package warpage, mechanical stress, and assembly yield.
This means → TSMC must build a verification framework spanning material, package, and system levels. Any new material source must clear both package-level and system-level validation before entering mass production.
How is the development cycle being compressed?
Using CoWoS-L as an example, He said the previous generation took roughly two years to develop; the current target is one year — a reduction of about three-quarters.
This means → the traditional "design first, validate next, then ramp" serial model is breaking down. System integrators, suppliers, and equipment makers must begin validation in parallel during TSMC's qualification-planning phase.
In plain terms = instead of lining up one by one to pass each gate, everyone is now on the field at once, validating while they build. Whether this parallel model can fully replace the old serial approach is the central execution challenge for TSMC and its partners.
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