TSMC/ASML/Imec Complete 2D Transistor Integration Validation on 300mm Wafers
Alina Collins
TSMC, ASML, and Imec have achieved quasi-CMOS integration of 2D-material transistors on a 300mm wafer with 94% yield — the first time atomically thin channel materials have moved from the lab bench into a real semiconductor manufacturing flow.
What exactly did they demonstrate?
The three partners built both n-type and p-type transistors on the same 300mm wafer, using molybdenum disulfide (MoS₂) for NMOS and tungsten diselenide (WSe₂) for PMOS — a quasi-CMOS integration (putting both polarities on one wafer, the basic requirement for making chips).
Key specs: contacted poly pitch (CPP — the minimum spacing between adjacent transistors) down to 50 nm, minimum channel length 28 nm, equivalent oxide thickness roughly 2 nm.
Working-transistor yield hit 94%, defined as devices with an on/off current ratio above 10⁵. This means → not "a few devices worked in the lab," but "the vast majority on a full wafer switched correctly."
Why is the p-type device the critical bottleneck?
Making n-type transistors from 2D materials is relatively mature. The p-type side, however, has consistently fallen far short of lab benchmarks when built with fab-compatible processes — the biggest weakness of this technology path.
This time, the WSe₂-channel pFET reached performance close to the best lab-grade devices, and both polarities shut off cleanly at zero gate voltage. In plain terms = they not only "turned on" but also "turned off" — no unwanted leakage.
The breakthrough came from an inverted thin-film transistor (TFT) process flow: contacts are fabricated first, then the channel material is transferred on top — the reverse of the conventional sequence.
What role does EUV lithography play?
Previous 2D-channel devices on 300mm wafers were physically large and patterned with older lithography, unable to match the pitch targets of advanced nodes.
ASML's EUV lithography — etching circuits with extreme-ultraviolet light — delivered the resolution needed to shrink channel length to 28 nm via single-pass patterning, eliminating multi-exposure stacking and keeping the process simpler and more cost-controllable.
This reflects a broader trend: EUV is not just a tool for shrinking silicon transistors further — it is becoming a prerequisite for bringing new material systems into volume production.
Where is this technology headed?
Imec positions the result as a critical milestone on the "lab-to-fab" path for 2D-material transistors, targeting ultra-scaled logic, back-end-of-line integration (BEOL — the metal interconnect layers inside a chip), and wafer backside integration.
TSMC CTO Min Cao stressed that the collaboration is about de-risking and accelerating the transition of new channel materials from the paper stage to the manufacturable stage.
The decisive test still lies ahead: whether 2D materials can sustain near-lab-grade performance in an industrial mass-production environment, not just in a validation batch. Put simply = making one wafer work doesn't count — making ten thousand in a row work does.
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