TSMC CoWoS Capacity Approaching AI Demand, Yield Rate Exceeds 98%
Nashnova编辑部
TSMC's advanced packaging VP Jun He disclosed that CoWoS capacity — after doubling annually for several years — is close to meeting AI customer demand, with production yield steady above 98%. This means advanced packaging is shifting from a capacity bottleneck to a technology endurance test: the race is no longer about building enough lines, but about holding near-perfect yield on ever-more-complex structures.
Has capacity finally caught up?
Jun He told the OCP Asia-Pacific Summit in Taipei on August 11 that CoWoS capacity has been roughly doubling each year and is now "very close" to meeting customer demand — but not quite there yet.
Production yield is stable above 98%, with some products reaching 99%.
This means → capacity is no longer the biggest bottleneck, but the gap between "close" and "met" still leaves AI chip customers short of all the packaging they want.
98% yield sounds high — why is TSMC still anxious?
He stated explicitly that yield above 98% is the precondition for introducing any new 3DIC technology — not a target to chase after ramp.
In plain terms = every CoWoS package carries more expensive chips in a more complex structure. Each added feature multiplies the failure probability — if yield isn't high enough, new technology simply cannot go live.
At data-center scale, where thousands of packages run in parallel, keeping overall failure rates acceptable requires per-component quality standards above automotive grade. This reflects a mental-model shift: advanced packaging quality is now judged at the system level, not the chip level.
What is changing inside the interposer?
The interposer — the layer connecting chip to chip — used to be a passive wiring layer. It is now absorbing active functions: bridges, integrated voltage regulators, capacitors, and a growing number of silicon photonics components (devices that carry signals with light instead of electricity).
He noted that electrons excel at computation, but for signal transport, photons are far more energy-efficient — and that is where AI systems are heading.
This means → packaging is no longer just "putting chips together." It is becoming an active system — the interposer itself does work, not just routing.
What problem does chiplet disaggregation actually solve?
Two forces drive the architecture forward. First, economics: chiplets (splitting one large chip into several smaller ones manufactured separately) break past reticle-size limits and separate analog content from compute, cutting the cost of migrating to the latest process node.
Second, performance — what He called 3DIC's "hidden gem" for the system community. Multi-chip packages allow die-to-die matching, compressing the natural statistical spread of device performance, raising consistency, and salvaging dies that would otherwise be scrapped.
In plain terms = think of grading eggs by size — pairing chips with similar performance makes the whole package more consistent, and "rescues" some chips that would have been thrown away.
What does the scale roadmap look like?
TSMC is currently in volume production at 5.5× reticle size and plans to reach 14× reticle size by 2029, releasing one new CoWoS generation each year.
On the 3D axis, SoIC hybrid bonding — joining chips directly face-to-face — delivers 50× the interconnect density and 5× the power efficiency of conventional stacking. 6 µm bond pitch entered production last year; 4.5 µm pitch (enabling A14-on-A14 stacking) is planned for 2029.
This means → packaging area and 3D stacking density are advancing in parallel, and every step must hold yield above 98%. That is the real test of TSMC's advanced-packaging moat.
How deep is TSMC's moat, really?
He used a vivid analogy for die-matching: "I run ten advanced packaging fabs every day. Sometimes I feel like I'm running the world's largest matchmaking service — customers give me an algorithm to find each die's soulmate, and I match, deliver, and boost system performance across a global manufacturing network."
This reflects that the barrier in advanced packaging is not just equipment and process — it also includes data-matching capability across a large-scale manufacturing network.
Whether TSMC can sustain near-perfect yield on ever-larger packages while iterating once a year is the key validation of how deep that moat really goes.
Content is for reference only, not financial advice.