TSMC Restarts Taoyuan Longtan Phase 3, Debuts CoPoS Advanced Packaging
nashnova research
TSMC's Longtan Phase 3 park — shelved for nearly three years — has been approved to restart, with the 104.65-hectare site set to prioritize CoPoS advanced packaging as a new expansion node after AP7 and AP8, responding directly to AI's relentless squeeze on packaging capacity.
Why is Longtan Phase 3 restarting now?
Taiwan's National Development Council approved the Longtan Phase 3 development plan on September 17, 2026. The park covers 104.65 hectares.
The project had been shelved for nearly three years; its restart coincides with AI chip demand pushing advanced-packaging capacity to the breaking point.
This means → TSMC has concluded that the packaging bottleneck is severe enough to warrant an entirely new campus, not just expansions at existing sites.
What is CoPoS — and why does it come first?
CoPoS — a technology that bridges multiple chips together on a silicon interposer and packages them as one unit — is Longtan Phase 3's lead deployment target.
TSMC's existing advanced-packaging stack includes CoWoS and SoIC, handling lateral chip tiling and vertical stacking respectively. CoPoS is the next-generation evolution.
In plain terms = CoWoS solves "placing chips side by side"; CoPoS aims to pack them tighter and connect them faster — as AI chips grow larger, packaging must keep pace.
How large is TSMC's packaging footprint today?
Existing facilities AP1 through AP6 remain in operation, while AP7 (Chiayi) and AP8 (Southern Taiwan Science Park) are expanding CoWoS and SoIC capacity.
Longtan Phase 3 sits adjacent to the AP3 complex and is expected to become another major packaging hub.
Pingtung's Haifeng park is also reported to be in early planning for advanced packaging use.
This reflects a deliberate multi-site strategy — TSMC is spreading packaging capacity across northern and southern Taiwan rather than concentrating it in one region.
What are partners picking up?
Vanguard International Semiconductor (a Winbond subsidiary) expects its Singapore 12-inch fab to begin production in January 2027, having secured a long-term interposer contract — the interposer is the middle layer connecting chips to the packaging substrate — from TSMC.
TSMC signed a five-year, $2 billion manufacturing agreement with GlobalFoundries, which will expand its Malta, New York plant as a U.S.-based interposer supply hub.
Amkor launched advanced packaging and testing cooperation with TSMC in the U.S. in 2024; ASE and SPIL are also absorbing overflow packaging orders.
This means → TSMC's own expansion still cannot meet demand, forcing it to offload part of the workload to partners — a clear signal of how tight capacity remains.
Why is AMD seeking alternative packaging routes?
AMD is advancing its EFB strategy — a packaging approach that uses bridge chips to interconnect multiple dies — working with ASE and SPIL on wafer-level 2.5D bridging.
In parallel, AMD is validating panel-level 2.5D EFB with Powertech Technology, aiming to reduce dependence on any single packaging source.
In plain terms = AMD does not want all its eggs in TSMC's basket — and the fact that it is hedging says everything about how constrained CoWoS capacity is.
What is happening on the front-end wafer side?
STSCP's F18 P9 and P10 phases are expanding 3 nm capacity; Hsinchu's F20 has four fabs targeting 2 nm and A14 process nodes.
Kaohsiung's F22 plans six phases focused on 2 nm and A16; the STSCP special zone adds five more fabs primarily for 2 nm.
Further out, the core site for sub-A10 nodes will be STSCP Shalun's F26, planned for 12 fabs.
This reflects a synchronized front-end and back-end expansion — the more advanced the chip, the more rigid the demand for advanced packaging becomes.
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