TSMC's CoWoS Capacity to Reach 200K Wafers/Month by 2027, with NVIDIA Accounting for 45%
Alina Collins
Morgan Stanley's latest report raises TSMC's year-end 2027 CoWoS monthly capacity forecast by 18% to 200,000 wafers, with total global CoWoS demand up 93% year-on-year — Nvidia, AMD, and Broadcom together consume over 80% of that capacity, underscoring just how hard AI demand is pushing the packaging bottleneck.
Why is the capacity forecast being raised?
TSMC's CoWoS monthly capacity estimate moves from 170K to 200K wafers, an 18% uplift matching roughly 60% year-on-year growth in the global AI XPU industry.
This means → real demand for AI GPUs and CPUs has outrun prior market expectations, forcing capacity plans to chase demand rather than lead it.
TSMC is expanding on two fronts: continued buildout at AP7, and converting 28nm/22nm lines at fab 15A to produce 55nm interposers — the silicon "bridge boards" that connect multiple chips inside one package.
Who is consuming the capacity? How much do the top three take?
Nvidia is projected to consume 1.222 million wafers in 2027, up 57% year-on-year, claiming roughly 45% of total demand. CoWoS-L accounts for 910K wafers (Blackwell and Rubin AI GPUs); CoWoS-R adds 130K for Vera CPUs, translating to 5.75 million CPU shipments.
AMD grows fastest — 530K wafers, a 308% year-on-year surge, roughly 20% share. MI455 leads via TSMC CoWoS-L; Venice CPUs shift to non-TSMC packaging, jumping to 270K wafers and 6.75 million CPUs, driven largely by Agentic AI workloads.
Broadcom takes 484K wafers, about 18% share. The bulk — 343K CoWoS-S wafers — goes to Google's TPU v7 (Ironwood) and v8i (SunFish), yielding roughly 4.168 million TPU chips.
What does Google's multi-track TPU strategy signal?
Google is running four TPU lines simultaneously in 2027: v8t (ZebraFish, designed by MediaTek, 3nm, 180K CoWoS-S wafers), v8i (SunFish, designed by Broadcom, 330K CoWoS-S), v9 (HumuFish, 2nm, packaged via Intel EMIB-T — not TSMC CoWoS), and inference-focused TriggerFish.
This means → Google is deliberately diversifying its packaging supply chain. Routing v9 through Intel is a direct hedge against TSMC CoWoS bottlenecks.
In plain terms = eggs in multiple baskets. Google taps TSMC, Intel, MediaTek, and Broadcom in parallel so no single supplier becomes a chokepoint.
How much goes to non-TSMC packagers?
ASE/SPIL and Amkor are projected to reach a combined 80K wafers/month by end-2027 — ASE/SPIL rising from 30K to 50K, Amkor from 20K to 30K.
Both focus on CoWoS-L and CoWoS-R formats, absorbing overflow orders such as AMD's Venice CPUs.
This reflects a simple reality: TSMC alone cannot supply enough capacity, and customers are pushing orders outward.
How large are AI wafer and HBM demand now?
The 2027 global AI wafer market is worth at least $47 billion, up sharply from $27 billion in 2026. TSMC's 3nm wafer price sits at roughly $27,300; 2nm at roughly $30,000.
Nvidia's Rubin R200 alone is expected to consume about 470K wafers, contributing roughly $12.8 billion in revenue. Vera CPUs add 228K wafers and about $6.2 billion.
On the memory side, global AI HBM consumption could reach 51 billion Gb in 2027, up from 31 billion Gb in 2026, as HBM4 and HBM4e enter mass adoption.
Where is the ceiling for TSMC's AI revenue?
Morgan Stanley projects TSMC's AI-related revenue — spanning general AI chips, custom ASICs, CoWoS/wafer testing, and AI server CPUs — to grow at a 60% CAGR from 2024 to 2029, exceeding $8.6 billion in 2027 and $12.1 billion in 2029.
This means → advanced packaging is shifting from a TSMC side business to a core revenue engine.
The report flags a key risk: whether this capacity allocation materializes depends on upstream links — HBM supply and ABF substrates (the critical board material used in advanced packaging) — keeping pace. A bottleneck in either could ripple downstream to shipment volumes.
Content is for reference only, not financial advice.