Wedbush: UMC May Benefit from Intel EMIB-T; Powerchip Semiconductor Enters Supply Chain
Claire Weston
Wedbush analyst Matt Bryson flags UMC as a major potential beneficiary of Intel's EMIB-T packaging push, while Powerchip has already entered the supply chain; with yields past 90% and costs over 40% below TSMC's CoWoS, a confirmed Google TPU packaging win would reshape the advanced-packaging landscape.
What is EMIB-T, and why is it suddenly in the spotlight?
EMIB-T — embedded multi-die interconnect bridge — is Intel's advanced packaging approach. It replaces TSMC CoWoS's large silicon interposer with small silicon bridges that link multiple chips together.
This means → packaging cost drops more than 40% versus CoWoS. Back-end production yield has crossed 90%, hitting the mass-production threshold, with volume ramp expected in 2026.
In plain terms = both methods stitch multiple chips into one package, but EMIB-T uses smaller, cheaper "glue" — and the pass rate is already high enough for the factory floor.
Who says this works? What is the evidence chain?
MediaTek CEO Rick Tsai's positive comments on EMIB yield are viewed by Bryson as "fully confirming" market speculation that Google's next-gen TPU will shift to Intel EMIB-T packaging. MediaTek is Google's core ASIC design partner for TPU, making its endorsement a key proof point.
MediaTek CFO David Ku stated on the earnings call that, based on all positive data to date, MediaTek is confident it will hit the production timeline — the current EMIB route no longer needs TSMC CoWoS as a backup.
This reflects a decisive upgrade: EMIB-T has moved from "fallback option" to MediaTek's primary path. Dropping the safety net is itself the strongest confidence signal.
UMC and Powerchip — what roles do they play?
Wedbush names UMC as a major potential beneficiary of EMIB-T progress. Bryson also cites a TrendForce report confirming that Powerchip Semiconductor Manufacturing has entered the Intel EMIB-T supply chain.
This means → Intel is expanding the EMIB-T supply chain beyond its own fabs, recruiting mature-node foundry partners to support volume production.
In plain terms = Intel cannot fill the capacity alone, so it is pulling in outside foundries — UMC and Powerchip are the reinforcements.
How big is MediaTek's AI ASIC revenue opportunity?
MediaTek management raised its 2027 AI ASIC market-share target from 10–15% to 15–20%. Against an addressable market of $80 billion, that implies potential revenue of $12–16 billion.
The first AI ASIC is set to enter mass production in Q4 2026, with a confirmed $2 billion revenue contribution. Citi is more bullish, projecting $18 billion in related 2027 revenue.
MediaTek is running a dual-packaging strategy — TSMC CoWoS and Intel EMIB-T — to serve different customers' large-scale AI chip designs.
What does this mean for Intel's foundry business?
JPMorgan argues that Intel's collaboration with Google should be limited to packaging, not wafer fabrication — TPU wafers will still be made by TSMC; Intel handles packaging only.
Even so, advanced packaging is one of the fastest-growing segments in AI chip manufacturing, and TSMC's CoWoS capacity has been chronically short. This means → Intel's EMIB-T is entering exactly the market with the widest supply-demand gap.
Intel Foundry Services last month named cybersecurity firm Fortinet as its first publicly identified external foundry customer. If the Google TPU packaging order lands, it would be IFS's most significant external win to date — and a critical proof point for Intel's IDM 2.0 transformation strategy.
Content is for reference only, not financial advice.