What does Huawei's Tao Law Paper Talk About?

In May 2026, He Tingbo, President of Huawei's Semiconductor Department, publicly presented the "Tao (τ) Law" in Shanghai and simultaneously released a lengthy paper. This is the first time a Chinese company has proposed a new principle to guide the development of the global semiconductor industry.

Let's start with a one-sentence conclusion:

Moore's Law is running out of steam, and Huawei proposes to replace the old path of "making transistors smaller and smaller" with a new metric — time constant τ (pronounced "Tao") — to redefine what "chip progress" means.

What is Moore's Law and why is it no longer sufficient?

Over the past 60 years, the semiconductor industry has advanced based on a simple rule: every two years, the number of transistors that can be packed onto a chip doubles, performance doubles, and costs are halved. This is Moore's Law. It has underpinned the entire modern computing industry — PCs, smartphones, cloud computing, AI, all of them have grown along this curve.

But this path is now encountering problems. After 7 nanometers, the performance improvements brought by simply downsizing transistors become increasingly marginal. Manufacturing costs soar dramatically; the design budget for a 2-nanometer node chip has exceeded 1 billion USD. The notion that "transistors become cheaper as they get smaller" no longer holds true, and at the most advanced nodes, there is even a reversal — the newer, the more expensive. For Huawei, there is an additional constraint: advanced lithography equipment is subject to export controls, and we cannot rely on purchasing the latest equipment to switch to new nodes.

Thus, He Tingbo posed a question in his paper: instead of continuing to ask "how small can transistors be made," why not ask "what should be optimized"?

The τ Law: Switching to a New Measure of Progress

Huawei's answer is to use "time" instead of "area" as the core metric for measuring chip progress. This time is the τ (Greek letter, pronounced "Tao") defined in the paper.

Why is time more fundamental than area? The paper provides a clear explanation: the reason why performance improves as transistors get smaller is, essentially, because signals travel faster, switches operate faster, and data transmission takes fewer detours — ultimately, "time" is reduced. Spatial reduction is merely a tool for compressing time, not the goal itself.

Given this, let's directly aim for time. The τ metric can measure everything from the most minute transistor switches to the response times of entire AI data centers. Transistor layers correspond to the picosecond level, circuit layers to the nanosecond level, chip layers to the microsecond level, and the entire systems layer is in milliseconds or even seconds.

The core proposition of the τ Law is that continuous compression of τ at every level represents progress. Advanced process nodes are one means, but not the only means, and no longer the most important means.

The First Real-world Case: "Logic Folding" of Mobile Phone Chips

This is not just talk. The paper presents two examples that have already been mass-produced, with the first being mobile SoC, or Kirin chips.

Background of the issue: Huawei cannot use the latest lithography machines and cannot easily move to the next process node. However, users expect performance improvements in Kirin chips every year. What to do?

Huawei's answer is called LogicFolding, which in Chinese is known as 逻辑折叠. Traditional chips are planar — transistors are laid out on a single plane, and signals are routed through the metal layer above, twisting and turning. The longer the wire, the slower the signal, and the larger the τ. The logic folding approach is straightforward: it divides the plane into two layers, with key pathways spread across both layers, connected by ultra-fine spacing hybrid bonding, allowing signals to no longer have to travel long distances. It's like folding a piece of paper, taking two points that were 10 centimeters apart at the ends and bringing them right next to each other after folding.

The measured data on the Kirin 2026 chip is quite specific. Transistor density increased from 155 to 238 MTr/mm², a 55% increase in a single generation, a level of improvement that used to take three years. The performance core power efficiency has been improved by 41%, the highest frequency has been increased by about 13%, and this year's CPU core has returned to 3.1GHz. SRAM operating frequency has been increased by over 40%