ASML Partners with Major Chipmakers to Advance High NA EUV Large-Format Reticles
nashnova research
ASML is teaming up with TSMC, Samsung, and SK Hynix to upgrade its next-gen High NA EUV lithography tools with larger reticles, removing the chip-size bottleneck for massive data-center processors, with volume production targeted for 2033.
Chips keep getting bigger — where exactly is the bottleneck?
Data-center chips from Nvidia and Google already approach the ~800 mm² maximum print area of current EUV tools.
ASML's High NA EUV — the next-generation lithography system that etches finer circuit features — uses a smaller reticle (the "negative" that projects circuit patterns), so it actually cannot print chips as large as today's biggest designs.
This means → the upgrade in precision comes with a downgrade in size — a real contradiction for data-center chips that need both.
How does ASML plan to fix this?
ASML will scale the High NA EUV reticle up to a larger format (12-inch class), enabling the new tools to produce chips equal in area to today's largest.
ASML CTO Marco Pieters told Reuters: "If the industry can pull this off, throughput on these systems will rise 40%."
In plain terms = a bigger reticle means a bigger printable area per exposure, so each machine produces more chips per hour — a breakthrough in both capacity and chip size.
When are TSMC, Samsung, and SK Hynix joining in?
TSMC: plans to use High NA EUV in advanced-node volume production from 2030.
Samsung: plans to bring High NA EUV into DRAM volume production by 2028.
SK Hynix: evaluating membership in the 12-inch reticle consortium, targeting 2028 for High NA EUV DRAM volume production.
This reflects a split in pace — memory makers (Samsung, SK Hynix) are moving faster than the leading logic foundry (TSMC).
Is this timeline realistic?
ASML's own roadmap: demonstrate a pilot line with the larger reticle in 2031, reach volume-production readiness by 2033.
Intel already uses High NA EUV for laptop-chip production, but TSMC and Samsung have not yet deployed it at scale.
This means → a two-year window separates "pilot line" from "production-ready," and whether leading foundries adopt on schedule will be the key validation milestone for the semiconductor-equipment supply chain over the coming years.
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