Chinese Academy of Sciences Explores Sub-3nm Chip Process Path Using DUV Lithography
nashnova research
CAS has completed early integration of sub-3nm GAA transistors using existing DUV lithography — charting an alternative process route around the EUV export ban, though production-ready manufacturing remains far off.
What exactly did they build?
The Institute of Microelectronics at the Chinese Academy of Sciences (CAS) completed early integration of stacked nanosheet GAA transistors — a structure where ultra-thin silicon sheets are stacked and the gate wraps the channel on all four sides.
The critical detail: the work used existing DUV equipment, not EUV. This means → the entire process route bypasses the EUV machines China cannot buy.
Researcher Ye Tianchun (叶甜春) described it as "a brand-new early MOS transistor process path for China's sub-3nm advanced manufacturing."
Why does bypassing EUV matter?
EUV lithography — etching chip circuits with extreme-ultraviolet light — is built exclusively by the Netherlands' ASML and is considered essential for nodes below 7nm.
U.S. export controls ban ASML from selling EUV tools to Chinese customers. In plain terms = on the conventional path, Chinese fabs are locked out below 7nm.
The CAS route aims squarely at that gap: use the tools already available to produce devices that normally require EUV.
How far is this from mass production?
The work is still at an early stage — what has been demonstrated is device-level integration, not a full process flow ready for a fab line.
This means → between "building a transistor" and "shipping chips at volume," yield, reliability, and cost engineering all remain unsolved.
This reflects a directional milestone in China's alternative-route efforts, but whether early device integration can translate into real manufacturing capacity is still an unproven question.
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