DDR5 Profit Margins Approaching HBM Levels as Samsung and SK Hynix Shift Production Capacity
N.R. Finch
Samsung and SK Hynix are redirecting incremental DRAM capacity from HBM toward DDR5 and other conventional memory, because DDR5 margins have in some cases surpassed HBM — a signal that the two-year "HBM-first" playbook is fraying.
How did DDR5 become more profitable than HBM?
The HBM-to-DDR5 price multiple was previously around 4–5×. By end of 2026 it is expected to narrow to 1–2×. Per-wafer revenue for some 64GB DDR5 RDIMMs — a server-grade memory module format — is now estimated to exceed HBM.
This means → HBM's pricing halo is fading. On a per-wafer basis, DDR5 already matches or beats HBM profitability.
Two structural reasons drive this. First, DDR5 contract prices reprice faster — when supply tightens, quotes adjust almost immediately. HBM is mostly sold on annual or long-term agreements with locked pricing, so spot-market rallies pass the supplier by. Second, DDR5 skips the stacking and bonding steps HBM requires, cutting manufacturing cost.
In plain terms = HBM sells at a higher sticker price but that price is locked in and the process is expensive. DDR5 sells cheaper per unit but reprices instantly and costs less to make — on a total-margin basis, DDR5 wins.
What exactly are Samsung and SK Hynix doing?
According to Korean industry media, both chipmakers have prioritized conventional DRAM when allocating incremental output and adjusting wafer product mix since Q1 2026 — while keeping committed HBM shipments intact.
Samsung has not exited HBM. It began mass-producing and shipping HBM4 in February 2025 and says it is expanding HBM4 capacity. This means → the shift is not "abandoning HBM" but routing incremental and flexible capacity to the higher-margin DDR5 line.
SK Hynix is reportedly slowing parts of its HBM3E-to-HBM4 line conversion, freeing capacity for conventional DRAM. HBM already accounts for over 40% of SK Hynix revenue, but Q1 data shows conventional DRAM operating margins ran more than 15 percentage points higher than HBM.
How big could the supply gap get?
Meritz Securities analyst Kim Sunwoo estimates that in H2 2026, DRAM suppliers can meet only about 75%–80% of demand. By 2027 the fill rate may drop to the 60% range, or roughly 70% after stripping out speculative orders.
This means → tilting capacity toward DDR5 will not close the market gap — on the contrary, overall DRAM supply is set to tighten further, keeping upward pressure on prices.
This reflects a deeper dynamic: memory makers are actively tightening the supply side (slower HBM expansion + capacity steered toward the most profitable SKU), while the demand side (servers, AI infrastructure) keeps growing. The squeeze widens from both ends.
Why is Samsung simultaneously scaling up test capacity?
Samsung began adopting Exicon's CLT system — a chamber-based, low-frequency memory tester that places multiple test boards inside a chamber to test large batches of DRAM chips simultaneously — in 2025, and added Neosem as a supplier in 2026.
Exicon holds a ₩49.85 billion contract with Samsung for CLT and SSD test equipment; Neosem disclosed an ₩8.6 billion CLT contract. Both run through December 31, 2026. Per a Daishin Securities report, Exicon shipped 10 systems in 2025 and is projected to deliver 15–20 in 2026.
In plain terms = one Exicon CLT system tests 11,520 devices at once — over 20× the throughput of the legacy foreign equipment it replaces. The logic is straightforward: if DDR5 shipments are about to surge, back-end testing cannot be the bottleneck.
What does this mean for the market?
The structural gap between DDR5's pricing elasticity and HBM's locked long-term agreements is the key variable to watch as margins for the two product lines diverge. If DDR5 prices keep climbing, the capacity tilt will accelerate further.
This means → the investment thesis for memory is splitting. It is no longer enough to simply "bet on HBM." The DDR5 supply chain — especially test-equipment names like Exicon and Neosem — becomes a new focal point.
This reflects a turning point in the AI hardware cycle: when HBM capacity is locked up by long-term contracts and margins are eaten by process costs, the supposedly "conventional" DDR5 turns out to be the product with greater elasticity and fatter profits.
Content is for reference only, not financial advice.