Gelsinger Slams HBM as "Terrible," SK Hynix: Not the Ultimate Answer
Nashnova编辑部
Former Intel CEO Pat Gelsinger publicly called HBM a 'terrible' memory technology at the RAISE summit in Paris. SK Hynix responded swiftly — acknowledging the limits but insisting HBM remains the best available option for AI today — as the race for post-HBM architectures begins.
Why did Gelsinger call HBM 'terrible'?
HBM — high-bandwidth memory, a technology that stacks multiple DRAM chips vertically like a sandwich — has a core problem: heat. It builds up between chip layers, creating a "thermal sandwich" effect.
This means → the more layers you stack, the harder it is to cool the chips in the middle. A physical ceiling caps performance.
Gelsinger also pointed out that producing 1 bit of HBM effectively sacrifices 4 bits of conventional memory capacity — poor bit efficiency, power efficiency, and bandwidth efficiency.
His conclusion was blunt: HBM is not good memory technology — it is simply the least-bad option for AI's near-term needs.
Does SK Hynix agree?
SK Hynix VP Kim Ho-sik partly agreed at the same panel: HBM has real limits in thermal management, I/O, and cost — and is not the final answer to the memory bottleneck.
But he stressed a more fundamental point: AI chips process data far faster than memory can feed it. That gap is intrinsic to AI inference, not something a different memory type alone can fix.
In plain terms = the memory bottleneck is a "constitutional" problem for AI. HBM is the most effective symptom relief available, but it does not cure the underlying condition.
Kim also revealed that SK Hynix is already researching next-stage solutions beyond HBM.
Who is building what for the post-HBM era?
Intel is exploring Z-Angle Memory (ZAM) and Cross-Batch Memory (XBM) — new architectures that use different chip layouts and interconnects to break through HBM's structural limits.
Nvidia is taking a different path: expanding the ultra-fast SRAM cache inside GPUs, reducing dependence on external memory bandwidth.
This reflects a split in how the two giants diagnose the bottleneck — Intel believes the memory architecture itself must change; Nvidia believes the compute side can absorb part of the load.
Is the memory industry's power shifting?
The old logic: Samsung, SK Hynix, and other memory makers decided what to produce first, then supplied it to customers.
The emerging trend: Nvidia, AMD, and other AI chip designers define system requirements first, and memory makers develop products accordingly.
This means → power in the memory industry is shifting from "those who make memory" to "those who use it" — whoever can define the system bottleneck gets to define what next-generation memory looks like.
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