Goldman Sachs: China's Advanced Chip Gap to Narrow from 92% to 34% by 2035
Nashnova编辑部
Goldman Sachs projects China's advanced-chip supply gap will shrink from 92% in 2025 to 34% by 2035, driven by SMIC's aggressive expansion and yield improvements — but a structural bottleneck in lithography equipment means full self-sufficiency remains out of reach within this decade.
How does a 92% gap shrink to 34%?
Goldman estimates China's domestic supply of 7 nm-and-below wafers — the processes used for flagship phone chips and AI accelerators — will grow at a 46% compound annual rate from 2025 to 2035, far outpacing 17% demand growth over the same period.
By 2035, monthly supply is projected at 410,000 wafers against demand of roughly 619,000. Supply is catching up faster than demand is rising, so the gap narrows.
This means → China is not closing the gap entirely — it is shrinking the distance it falls short. A decade from now, nearly one-third of advanced chips will still depend on external sources.
What does SMIC's expansion plan look like?
Goldman's key assumption: SMIC adds 30,000–50,000 advanced-process wafers per month each year from 2026 to 2031, then 20,000 per year through 2035.
The yield assumption — the share of chips on each wafer that actually work — is equally aggressive: rising from 23% in 2026 to 50% by 2030 and 75% by 2035.
In plain terms = today, only 23 out of every 100 chips come off the line usable. Goldman is betting that figure reaches 75 within a decade — this is the single variable the entire forecast hinges on.
How far behind TSMC does that leave SMIC?
TSMC began mass-producing 7 nm chips in 2018. Its current yield consistently exceeds 90%.
Even if SMIC hits its 75% target by 2035, that is still more than 15 percentage points below where TSMC stands today.
This means → capacity numbers are converging, but the number of usable chips per wafer remains far apart. Volume is catching up; quality is not.
Why can't the gap close to zero?
Goldman explicitly flags lithography equipment — the machines that "print" circuit patterns onto wafers — as the structural bottleneck blocking full semiconductor independence.
No matter how fast capacity ramps, without access to cutting-edge lithography tools the process ceiling stays fixed. That is the fundamental reason the gap holds at 34% rather than reaching zero.
This reflects a deeper reality: China's semiconductor catch-up is a catch-up with a ceiling, and the pace of breakthroughs in domestic equipment determines how high that ceiling can rise.
Content is for reference only, not financial advice.