Google Accelerates Custom AI Chip Release Cadence, Supply Chain Pressure Rises in Tandem
nashnova research
Google has compressed its TPU release cadence to two generations per year, forcing the entire supply chain to keep pace — but bottlenecks in memory, power, cooling, and PCBs are surfacing simultaneously.
How fast is the chip cadence now?
Google AI-infrastructure SVP Amin Vahdat said TPU releases have moved from once every two years → once a year → twice a year in 2025.
The two latest chips are TPU 8t (training) and TPU 8i (inference), both launched this year. Google's first TPU shipped in 2015.
This means → iteration frequency has quadrupled in a decade, and Vahdat expects it to keep rising.
Can the supply chain keep up?
Vahdat acknowledged that bottlenecks are emerging simultaneously across memory, PCBs, high-voltage power supplies, liquid-cooling systems, and AI racks.
His words: "In the morning it's one problem; by noon it's another" — the moment you relax about one bottleneck, the next one appears where you least expect it.
In plain terms = no matter how fast the chips come, if power, cooling, and boards can't keep up, the machines don't ship — the weakest link sets the real delivery pace.
What has Google done on the network side?
Google has integrated Ethernet switch functions directly onto each chip, enabling chip-level compute-network coordination at lower power.
The wide-area network now supports one million TPUs working together via a three-tier architecture: supercomputing clusters (~10K TPUs) → data-center fabric (~100K) → cross-DC interconnect (million-scale).
This means → Google's edge is not just single-chip performance — it is the systems engineering to wire a million chips into one network.
How central is the Taiwan supply chain?
MediaTek co-designs the chips. TSMC handles wafer fabrication. Foxconn, Quanta, and Inventec assemble servers. Broadcom and Marvell are deep chip-development partners — Taiwan spans nearly every step from TPU design to final assembly.
Alphabet participated in MediaTek's latest $3.9 billion convertible-bond offering; Nvidia also joined.
Vahdat called Taiwan Google's largest AI-infrastructure R&D center outside the U.S., and Google plans to expand its Taiwan office space by 60%.
What does selling TPUs externally mean?
Google announced it will sell TPUs to outside customers — some sales have already begun — shifting its rivalry with Nvidia from "captive vs. merchant" to a direct, head-to-head contest.
Yet Google still buys Nvidia GPU servers for parts of its data-center buildout. This reflects that even with an accelerating in-house roadmap, it cannot fully replace Nvidia in the near term.
Alphabet raised its 2026 capex guidance to $195–205 billion for next-generation AI data centers.
How will foundry partnerships change?
Google is actively seeking to broaden and diversify its foundry partners: it has explored advanced packaging with Intel, and is reportedly in talks with Samsung Electronics over advanced-node capacity for future CPUs.
In plain terms = TSMC remains the core, but Google doesn't want all its eggs in one basket — when chips ship twice a year, capacity risk must be spread.
This means → Intel's and Samsung's advanced-node businesses may pick up incremental orders from Google, and the foundry landscape is being reshaped by the sheer pace of AI-chip iteration.
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