Google May Adopt CoWoS Packaging as Backup for 2027 TPU
nashnova research
Google is evaluating TSMC's CoWoS packaging as a fallback for its next-gen TPU after Intel's EMIB-T hit yield problems; a switch would deepen TSMC's dominance in AI chip packaging.
What is Google's next TPU project?
Codenamed "Humufish," the next-generation tensor processing unit — Google's custom AI chip — targets mass production by late 2027, with MediaTek as the ASIC design partner.
The original packaging plan calls for Intel's EMIB-T — an embedded multi-die interconnect bridge that links multiple chiplets through a silicon bridge.
This means → Google initially bet on Intel's packaging capability, not the more widely adopted TSMC route.
Why is a backup plan on the table now?
One reason: EMIB-T substrate yields are lagging — the share of usable parts coming off the line is too low.
Insufficient yield directly threatens the production timeline — no matter how good the chip design, packaging bottlenecks block shipments.
In plain terms = Intel's approach works on paper but hasn't proven out on the factory floor.
How does the CoWoS alternative differ?
CoWoS — Chip on Wafer on Substrate, a wafer-level advanced packaging method — is led by TSMC and already used at scale by Nvidia and other major AI chip clients.
This means → CoWoS offers far greater manufacturing maturity and capacity certainty than EMIB-T; choosing it means choosing the proven path.
If Google ultimately switches, TSMC's near-monopoly in AI accelerator packaging would tighten further.
Is anything decided yet — and what's the key variable?
The project remains in the technology-route evaluation phase; no final packaging decision has been made.
The decisive variable is clear: whether Intel can raise EMIB-T yields to production-grade before the late-2027 deadline.
In plain terms = Intel still has a window to fix the problem, but that window is narrowing — Google is already looking at other options.
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