Morgan Stanley: HBM Shortage Drives Nvidia Rubin Ultra Tiered Configuration; China Super Nodes Shift to NPO Interconnect
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Morgan Stanley's supply-chain checks show Nvidia's next-gen flagship GPU Rubin Ultra will ship in tiered SKUs due to HBM capacity shortfalls, while Chinese GPUs pivot to NPO interconnect under fab-process constraints — two compute roadmaps diverging around packaging and optical links.
Why is Rubin Ultra splitting into high and low tiers?
HBM — high-bandwidth memory, the ultra-fast memory that feeds data to GPUs — is in short supply. The premium SKU gets HBM4E 8Hi; lower-tier variants fall back to HBM4 12Hi or 8Hi. This means → Nvidia is forced to trade off between peak performance and shippable volume.
Morgan Stanley flags that a memory downgrade hits the decode phase (where a model generates answers token by token) far harder than the pre-fill phase (where it ingests the prompt in one pass). Long-context large models are especially sensitive.
The flip side: less memory per die → the same HBM output cuts into more dies → total chip shipments actually rise. Supply-chain players that profit from volume, not per-chip spec, stand to benefit.
Why is the Kyber rack delayed, and why does CPO matter?
Nvidia's Kyber blade server — first shown at GTC 2025 — is stalled by unresolved PCB and thermal issues. The first-generation Rubin Ultra server rack will likely stick with the existing Oberon NVL72 design.
Scaling to NVL576 depends on CPO — co-packaged optics, which builds the optical transceiver directly into the chip package so data never has to travel out over copper before converting to light. Morgan Stanley sees CPO as Nvidia's key performance differentiator over Chinese alternatives.
In plain terms = Kyber is the "ideal chassis" but not ready. Nvidia runs the new chip on the old platform; CPO is the real card that pulls ahead.
What path are China's super-nodes taking?
To run models exceeding 2 trillion parameters, Chinese GPU makers have rolled out "super-node" architectures — networking large numbers of domestic GPUs into a single logical compute unit.
Foundry-process constraints mean domestic GPU SerDes — the high-speed serial interface between chips — likely tops out at 100 Gb/s per lane, below Nvidia's level.
This means → rack-to-rack interconnect relies on NPO — near-package optics, where the optical module sits close to the chip but outside the package — rather than Nvidia's in-package CPO. This reflects a widening fork in the US-China compute race: in-package optical interconnect vs. near-package optical interconnect.
Google TPU is ramping — who is taking the orders?
Morgan Stanley forecasts Google TPU shipments at 3.7 million units in 2026 and over 7 million in 2027 — nearly doubling year on year.
King Yuan Electronics (KYEC), a chip test and packaging house, is a direct beneficiary: TPU-related work is expected to account for 7%–8% of KYEC's 2026 revenue and slightly above 10% in 2027, covering final test and some wafer probing.
Add Google's in-house CPU (2026: 1.5 million units; 2027: 3 million), and Morgan Stanley estimates Google-related demand will reach 10%–15% of KYEC's total 2027 revenue.
How far along is MediaTek's ASIC ambition?
MediaTek's guidance targets 15%–20% ASIC market share by 2027, broadly in line with Morgan Stanley's prior estimate.
MediaTek's 3 nm AI ASIC TPU is expected to require burn-in testing — running the chip under elevated temperature and voltage before shipment to screen out early failures.
This reflects an industry-wide trend: as AI chip power draws climb and reliability stakes rise, burn-in testing is shifting from optional to mandatory.
Do the 2027 chip and power numbers add up?
Morgan Stanley back-calculates from TSMC's CoWoS — wafer-level packaging — capacity: roughly 19 million chips shipped in 2027. At an average of 2 kW per GPU/ASIC, that implies about 38 GW of power capacity needed. Power infrastructure remains the global bottleneck.
Shipment cadence: Blackwell at 5.4 million units in 2026; Rubin plus Rubin Ultra near 7 million in 2027, with Rubin NVL72 rack shipments potentially hitting 90,000 units.
The market's earlier Blackwell "inventory" concern is, in Morgan Stanley's view, mainly supply-chain buffer stock that will be fully absorbed in 2026. Rubin will likely repeat the pattern: volume ramp in Q3 2026, rack shipments starting Q4.
Content is for reference only, not financial advice.