NVIDIA Feynman Advances TSMC A16 Process and CPO Mass Production
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Nvidia has locked in H2 2028 as the mass-production target for its Feynman platform, pressuring TSMC to simultaneously scale A16 process capacity and co-packaged optics — a timeline that pulls the entire supply chain from chip fabrication to optical interconnects into an intensive expansion cycle.
What exactly is Feynman upgrading?
Feynman will adopt TSMC's A16 node — an upgraded process built on 2 nm-class technology — and expand the use of SoIC, TSMC's 3D chip-stacking packaging method.
Interconnect bandwidth is the headline metric: Blackwell racks deliver roughly 130 TB/s → Rubin 260 TB/s → Rubin Ultra 520 TB/s → Feynman is expected to exceed 1,000 TB/s, entering the 1 PB/s class.
This means → bandwidth nearly doubles with each generation, and Feynman leaps into petabyte-scale territory. The demand on chip-to-chip data transport is fundamentally different from today's architecture.
In plain terms = chips used to move data on a "highway"; Feynman demands a "bullet train" — nearly 8× faster — so the road itself (packaging and optical interconnects) must be rebuilt to match.
Why is co-packaged optics (CPO) the linchpin?
CPO — placing the optical-electrical conversion module inside the chip package instead of on an external circuit board — is the core technology path enabling Feynman's 1 PB/s bandwidth.
TSMC is developing its COUPE technology: using SoIC to integrate an EIC (electronic integrated circuit) and a PIC (photonic integrated circuit) in 3D, forming an "optical engine."
This means → optical-electrical conversion moves from a rack-level external module into the package itself. Signals complete the electrical → optical → electrical loop at the chip level, sharply cutting latency and power consumption.
How intense is TSMC's capacity pressure?
TSMC is accelerating construction at its Chiayi AP7 and Nanya AP8 sites while pre-deploying SoIC, CoWoS-L, and next-generation CoPoS lines. Cleanroom fit-out and equipment installation have been told to "catch up" with the schedule.
Even so, capacity cannot fully meet customer demand. Siliconware (SPIL) is the primary subcontractor for Nvidia orders and is also expanding CoWoS and CPO capacity at its Erlin site.
Revenue from U.S. clients — including Nvidia — now exceeds 70% of TSMC's total. This reflects a reality: TSMC's expansion cadence is effectively being driven by Nvidia's product roadmap.
Where is Nvidia spending its money?
Since 2026 Nvidia has deployed over $40 billion across the AI ecosystem — a major bet on OpenAI plus investments in Intel, CoreWeave, Marvell, Lumentum, and Coherent.
The footprint spans AI models, wafer fabrication, cloud data centers, and optical communications. This means → Nvidia is no longer just selling GPUs; it is using capital to lock down every critical link from "making the chip" to "moving the data."
Nvidia has also partnered with Apollo, BlackRock, Blackstone, Brookfield, Goldman Sachs, and KKR to build an AI-infrastructure "financing platform," targeting over $500 billion in third-party capital to help customers buy GPUs and build data centers.
What does this mean for the supply chain?
Whether Feynman's production timeline holds is the key milestone validating TSMC's A16 node and CPO packaging at volume-production scale.
In plain terms = Feynman is not just one company's product launch — it is a "stress test" for the entire advanced-packaging and optical-communications supply chain. On-time delivery determines the real size of this cycle's equipment and materials order wave.
This reflects a deeper shift: the bottleneck in the AI compute race is moving from "chip design" to "chip manufacturing and packaging." Whoever gets capacity running first holds the ticket to the next round.
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