Rinto Tech Plans Mass Production of World's First Panel-Level AI Chip Packaging Line by 2027
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Taiwan's Powertech Technology (力拓科技) plans to start mass production on the world's first panel-level AI chip packaging line in Hsinchu as early as early 2027, investing over NT$70 billion (~US$2.2 billion). This means → Powertech could beat TSMC to production on a packaging technology seen as key to breaking AI compute bottlenecks.
What is panel-level packaging, and why does it matter?
Traditional chip packaging works on round wafers. Panel-level packaging uses large rectangular substrates instead. In plain terms = chips move from a "round plate" to a "big square table" — more area, more room to integrate different chips into a single package.
This paves the way for larger-scale AI compute systems: bigger packages, more integration, higher performance ceilings.
TSMC's advanced packaging still runs on round wafers. Its own panel-level effort — known in the industry as CoPoS — remains in development. This means → if Powertech hits its timeline, it will be first to production on this approach.
Why does Powertech believe it can pull this off?
Powertech is the world's largest memory chip packaging and testing contractor, serving Micron, Kioxia, and SanDisk — deep packaging expertise built over decades.
The company began panel-level packaging R&D back in 2016. This production plan is the payoff of nearly a decade of groundwork.
Chairman Tsai Tu-kung said: "This is the biggest bet of my life. We've been working toward today for a long time." This reflects a management team that sees panel-level packaging as the strategic pivot from memory packaging into AI advanced packaging.
Who will be the first customers?
Industry sources say Broadcom and AMD are Powertech's main advanced-packaging clients and are expected to be the first adopters of panel-level packaging services.
Powertech has already announced a joint venture with Broadcom in Singapore, focused on high-end AI chips and advanced packaging, with the Singapore plant targeted for production around 2028.
This means → panel-level packaging is not a lab concept for Powertech — it already has named customers and a concrete deployment timeline.
How does TSMC see this, and what does it mean for the industry?
TSMC Chairman C.C. Wei has said he welcomes more players into the advanced-packaging market to give customers more options.
The backdrop: TSMC's own packaging capacity has been consistently strained by booming AI infrastructure demand. In plain terms = TSMC's packaging lines are already overbooked; another supplier absorbing some of that pressure is a net positive for the whole AI supply chain.
Whether Powertech can deliver on its 2027 timeline will be a critical test of whether panel-level packaging can become the answer to AI chip packaging bottlenecks.
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