Samsung Bets on zHBM, Targeting Performance 8x Beyond HBM5
nashnova research
Samsung disclosed its zHBM architecture — stacking memory directly on top of AI accelerators — targeting eight times HBM5 performance and up to three times better power efficiency. This means Samsung is shifting from making faster memory to redesigning where memory sits inside the system.
What problem is zHBM solving?
Today's HBM — high-bandwidth memory, the module that feeds data to AI chips — sits beside the accelerator in a 2.5D layout. Data travels a lateral path that burns power and caps bandwidth.
Samsung's zHBM stacks memory directly above the accelerator. Data moves vertically; the path shrinks dramatically. In plain terms = instead of passing files from the next room, you drop them straight through the floor.
This means → bandwidth ceiling and energy bottleneck improve simultaneously. Samsung's targets: roughly 8× HBM5 performance, up to 3× better performance per watt, and over 50% lower thermal resistance.
How does Samsung plan to build it?
The manufacturing core is wafer-on-wafer integration — aligning and bonding two full wafers — plus hybrid copper bonding, which fuses upper and lower circuits through copper pillars for denser, shorter interconnects.
Once memory sits atop the accelerator, each accelerator's bandwidth, capacity, and thermal needs differ. This means → memory can no longer be a one-size-fits-all product; it must be co-designed with the accelerator.
The zHBM architecture also allows custom IP in an intermediate layer between memory and accelerator, expanding capacity or tuning performance per workload. This reflects Samsung's aim to make zHBM a configurable platform, not just a chip.
What role does zNAND-O play?
Samsung is developing zNAND-O in parallel — a high-performance NAND architecture positioned between DRAM and conventional NAND storage. In plain terms = speed close to memory, capacity close to a drive, cost far below DRAM.
Samsung estimates that by 2030, workstation-class systems will routinely run models around one trillion parameters. Serving that entirely from DRAM would be prohibitively expensive; adding zNAND-O could cut memory cost to roughly one-sixth of a pure-DRAM setup.
Target specs: read latency under 3 microseconds, bandwidth above 200 GB/s, power below 10 watts at that bandwidth, with sample shipments planned for 2028.
Put together, what is Samsung's message?
zHBM addresses speed and efficiency — placing the fastest memory on top of the processor. zNAND-O addresses capacity and cost — housing bulk data in a cheaper but fast-enough tier. This means → together they form a layered memory system organized by how close data sits to the processor.
This reflects a broader pivot in Samsung's memory strategy: the room to boost performance by simply stacking more HBM layers is narrowing. Samsung is shifting focus to where memory goes, how deeply it integrates with compute, and how data distributes across tiers.
The critical milestone: whether zHBM reaches volume production on schedule will directly test this architecture's commercial viability.
The system-level target: what does 1,000 tokens per user per second mean?
Samsung VP In Dong Kim set a system-level goal at the AI Infrastructure Summit: raise AI response throughput from roughly 100 tokens per user per second to 1,000 tokens.
In plain terms = Samsung wants large-model answers to come back ten times faster — and that is not achievable through the chip alone; memory, packaging, and architecture must all move together.
This means → zHBM and zNAND-O are not isolated memory upgrades. They are the infrastructure blueprint Samsung designed to hit that system-level performance target.
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