Samsung Showcases LPDDR5X-PIM at Hot Chips 2026, Boosting AI Inference Speed by 2.28x
Nashnova编辑部
Samsung demonstrated working LPDDR5X processing-in-memory silicon at Hot Chips 2026, showing a 3.01× jump in Llama 3.1 8B inference throughput — a sign that edge AI devices may soon sidestep expensive HBM by computing inside cheaper memory.
Inference 2.28× faster — where does the speed come from?
Running Llama 3.1 8B on Samsung's own edge AI accelerator, LPDDR5X-PIM cut execution time from 12.3 seconds to 5.4 seconds — roughly 2.28× faster.
Inference throughput jumped from 27.0 tokens/s to 81.3 tokens/s, about 3.01× the baseline.
This means → same edge chip, no processor swap — just a memory upgrade — and AI response speed doubles or triples.
In plain terms = a large model that took half a second to "think up a sentence" on a phone or edge box now does it in under 0.2 seconds.
What is "processing in memory" actually doing?
PIM — processing in memory — moves part of the computation directly inside the memory chip, so data doesn't have to shuttle back and forth.
LPDDR5X-PIM achieves 614 GB/s of internal PIM bandwidth, versus just 76.8 GB/s on the conventional external DRAM path — roughly eight times wider inside.
This means → the bottleneck shifts from "not enough compute" to "data moving too slowly"; PIM computes right where the data lives, eliminating the transfer step.
Can it drop into existing systems?
Samsung kept the JEDEC-standard 561-ball package; the physical interface matches current LPDDR5X.
An "Address Align Mode" maps DRAM addresses to PIM instructions, so existing memory controllers need minimal changes.
In plain terms = for device makers this is "swap one component and go," not "redesign the board" — and that integration barrier is exactly what killed earlier exotic memory architectures.
Samsung has released a simulator, datasheets, and an SDK, available on request.
Why now? Because HBM costs keep climbing
Samsung cited data showing HBM's share of AI chip component spending rose from 52% in Q1 2024 to 63% in Q4 2025 — memory is eating more of the hardware budget every quarter.
Micron, presenting at the same conference, noted that HBM requires roughly three times the wafer area of DDR5, and that gap "is certainly not going to shrink."
This means → if every inference workload runs on HBM, the hardware bill becomes unsustainable; LPDDR5X-PIM targets the sweet spot — workloads that don't need HBM-class external bandwidth but still want faster throughput.
Can it replace HBM?
No. LPDDR5X-PIM's external bandwidth is far below HBM; high-throughput training still needs HBM stacks.
Samsung's positioning is precise: for inference workloads, compute part of the job inside memory, cut cross-interface data movement, and trade lower cost for higher effective throughput.
This reflects a broader memory-industry trend — no longer chasing a single metric (maximum bandwidth) but tiering by workload: HBM for training, PIM for inference.
Can we trust the numbers? What comes next?
All performance figures are Samsung's internal measurements, not independent benchmarks; the two configurations also produced different output, and accuracy tuning is still underway.
Next-generation LPDDR6-PIM is on the roadmap, with JEDEC standardization in progress.
In plain terms = the numbers look good, but they haven't been independently verified; whether speed and accuracy both hold up at mass-production scale is the real test.
市场有风险，内容仅供研究参考，不构成投资建议。