SEMICON 2026: Advanced Packaging Evolves Toward 3D Integration, CPO Testing Becomes Mass Production Bottleneck
nashnova research
Citi, Nomura, and UBS all reached the same conclusion at SEMICON Taiwan 2026: the capacity bottleneck for AI chips is shifting from front-end wafer fabrication to packaging, optical interconnects, and testing — with CPO test trade-offs likely setting the pace for next-generation volume ramps.
Three banks, one field trip — what did they all see?
The critical constraint in AI chip scale-up is moving downstream — from making the chip itself to packaging, connecting, and testing it.
This means → the "chokepoint" has shifted. Front-end wafer capacity is no longer the sole bottleneck; packaging, optical interconnects, and test are all queuing for expansion.
Each bank focused differently — UBS on TSMC's packaging roadmap, Citi on CPO manufacturing, Nomura on test equipment — but the conclusion pointed in the same direction.
How far has TSMC's packaging roadmap progressed?
TSMC's 5.5× reticle CoWoS — an advanced packaging method that tiles multiple chips onto one substrate — is in mass production with yields above 98%.
UBS raised its forecast for TSMC's end-2027 CoWoS capacity to 260,000 wafers/month; by 2028 the platform expands to 14× reticle and supports 20-layer HBM stacking (HBM is the high-speed memory tower sitting next to an AI chip).
In plain terms = bigger packaging area, taller memory stacks — all so a single AI chip can ingest more data in one pass.
TSMC is turning cautious on its H2 2027 expansion pace. Some processes may be outsourced to ASE, meaning advanced packaging capacity is spilling over to OSAT firms — the specialist test-and-package contractors.
Panel-level packaging and optical interconnects — why are they surfacing now?
TSMC's CoPoS panel-level packaging — scaling the substrate from wafer size to a 310 × 310 mm² panel — targets mid-2027 for process and equipment selection, 2028 for mass production. UBS says equipment vendors' confidence is growing.
On optical interconnects, TSMC showed its COUPE roadmap: 200 G/lane by 2026, 400 G/lane by 2030.
This reflects a fundamental mismatch: AI compute demand grows roughly 3× every two years, but chip-to-chip I/O bandwidth grows only about 1.4× — copper can't keep up, so the industry is switching to light.
What makes CPO manufacturing so difficult?
CPO — co-packaged optics, embedding optical engines directly inside a chip package — requires integrating EIC (electrical chip), PIC (photonic chip), lenses, and fiber/FAU in a single assembly.
Citi noted that active coupling — aligning the optical signal to a fiber in real time — demands live optical-power feedback and multi-axis precision positioning. Volume production needs major gains in alignment speed and automated bonding.
In plain terms = converting an electrical signal to light, then aiming it into a fiber thinner than a human hair — a lab can do it; doing it fast, accurately, and at factory scale is the hard part.
The "Insertion 2" debate — to test or not to test?
Nomura's focus is Insertion 2: the mid-process test step after EIC and PIC are bonded at wafer level but before final packaging.
Throughput at this step is currently low, and the supply chain is debating whether to skip it entirely. Nomura argues that dropping it shortens cycle time, but some defects can only be caught here — skipping means blame is harder to assign when problems appear later.
UBS expects the industry to gradually simplify Insertion 2 while increasing reliance on Insertion 3 — the finished optical-engine test performed on each individual unit.
Test efficiency vs. coverage — who gains the most pricing power?
Chroma ATE proposed at the show that CPO testing may shift toward a "shift-to-middle" model: for high-density switch packages, a single defective optical engine can scrap an entire CoWoS-level assembly.
This means → 100% known-good-die verification at Insertion 3 may become a hard prerequisite for mass production — not a question of "whether to test" but "you can't package without testing."
The trade-off between test efficiency and test coverage will directly determine pricing power for test-equipment makers; lead times for some equipment have already stretched to roughly two years, signaling that downstream demand is already front-running supply.
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