SK Hynix Builds HBM Co-Design Team in Silicon Valley, Adjacent to Nvidia and AMD
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SK Hynix is assembling an HBM architecture design team in San Jose, steps from Nvidia and AMD headquarters, to co-develop next-generation HBM with AI chip clients from the product-definition stage — a sign that the memory race is shifting from 'who can build it' to 'who locks in the customer first.'
Why move a design team to Silicon Valley?
SK Hynix is hiring HBM — high-bandwidth memory, the ultra-fast memory that feeds data to AI chips — architecture designers in San Jose, California, to work face-to-face with Nvidia, AMD, and other clients on next-gen HBM and 3D DRAM base-die design.
San Jose sits next to Santa Clara, home to Nvidia and AMD headquarters; Broadcom also operates there. This means → the team can coordinate technical issues in real time during development, then relay findings back to R&D in Korea.
In plain terms = instead of building chips in Korea and shipping them to the U.S., SK Hynix is sitting down next to the customer before the design is even final.
Why does co-design become essential after HBM4?
Earlier HBM generations involved some customization, but starting with HBM4, the base die will use advanced logic process nodes — the same manufacturing tech used for processors — blurring the line between memory and system chips.
AI accelerators are diverging in performance and architecture, each demanding different capacity, bandwidth, and power profiles from HBM. This means → jointly optimizing the AI chip and HBM from the start is far more efficient than developing them separately and integrating later.
In plain terms = HBM is no longer a generic part. It is becoming a bespoke companion built for each AI chip — miss the design phase and you cannot get in afterward.
What will this team actually do?
Job postings show new hires will handle DRAM and HBM circuit design, improving design quality and yield during development.
The team will also analyze product characteristics at wafer, KGSD — known-good stacked die, meaning tested and qualified stacked units — and packaging stages to ensure customer specs are met.
SK Hynix explicitly lists "developing advanced custom HBM architectures for future products" as a core responsibility. This reflects a unit that is not post-sale tech support but a design organization embedded in the customer's product-development cycle.
What does this mean for the competitive landscape?
Once HBM is co-developed for a specific client's AI chip, a rival trying to enter that supply chain later faces a significantly higher barrier.
This means → co-design is, at its core, a tool for locking in next-generation orders early — whoever enters the client's product-definition stage first becomes the hardest supplier to replace.
In plain terms = the rules of this race have changed. It is no longer about whose memory specs are better — it is about who gets a seat in the customer's meeting room first.
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