SK Hynix Publishes CPO Technology Roadmap in Nature Electronics
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SK hynix and researchers from the University of Virginia published a paper in *Nature Electronics*, unveiling for the first time the company's co-packaged optics (CPO) technology blueprint for next-generation AI interconnects — signaling a strategic shift from memory component supplier to system-architecture player.
AI chips keep getting faster — so why is overall performance hitting a wall?
The paper notes that HBM — high-bandwidth memory — solved the on-chip memory bottleneck. But as AI clusters scale to thousands of GPUs, data transfer between racks has become the new constraint, which the authors call the "bandwidth wall."
This means → no matter how fast a single chip gets, if data can't move between chips quickly enough, the whole system stalls.
The numbers: compute power roughly triples every two years, while interconnect bandwidth grows only about 1.4× over the same period. In plain terms = the highway keeps adding lanes, but the toll booths barely change — more traffic, worse congestion.
How does CPO break through this bottleneck?
CPO — co-packaged optics — integrates optical transceivers directly into the processor package, so chips exchange data via light signals instead of long-distance electrical signals. In plain terms = swapping a "copper telephone line" for "fiber broadband," installed right next to the chip rather than in a distant equipment room.
The paper sets three hard targets for next-generation AI infrastructure: per-node bandwidth exceeding 100 Tb/s, energy consumption below 1 pJ/bit, and chip-to-chip latency under 10 nanoseconds.
Co-author Kyusang Lee stated: "Even if compute chips become more powerful, overall system performance cannot improve if data transfer between chips cannot keep up. Replacing copper interconnects — which face inherent physical limits — with optical interconnects is the most promising path to future scalability."
What is the ultimate goal for optical interconnects?
The paper's longer-term vision: extend optical interconnects all the way to the memory interface. This means → not just chip-to-chip communication via light, but chip-to-memory links as well.
The proposed "photon-centric" architecture uses a photonic interposer — an optical bridge layer — to connect a processor resource pool directly to a memory resource pool, letting multiple AI accelerators share one large memory pool instead of each carrying its own.
In plain terms = today, every chip has its own small bookshelf; when books run out, it's stuck. The future model is a shared library — whoever needs data goes and gets it, boosting utilization and flexibility.
Why is SK hynix pursuing this?
Seunghoon Hong, head of SK hynix's AI infrastructure team and the paper's corresponding author, stated: "Memory companies are evolving from single-component suppliers into partners that help improve the competitiveness of customers' entire systems through technologies like CPO."
This reflects a strategic pivot — from HBM component vendor to system-level architecture participant. This means → SK hynix no longer aims to just sell memory chips; it wants a say in how AI systems are designed.
Publishing in *Nature Electronics* rather than an industry white paper is itself a signal: SK hynix is staking a claim in both academia and industry for its role in next-generation interconnect architecture.
How far away is commercialization?
Lee acknowledged significant challenges remain: "From integrating low-power photonic devices to developing coherence protocols and improving system reliability, the key is co-designing memory devices with controllers, photonic components, and packaging as an integrated system."
In plain terms = individual components can be built, but making all of them work together reliably inside a single package is the hardest engineering problem.
The market has already priced in the narrative: driven by the paper and a buyback plan, SK hynix surged more than 11% in early trading; China A-share CPO concept stocks rallied in tandem, with Taichen Light up over 12% and Zhongjing Electronics hitting the daily limit. This reflects high market sensitivity to the CPO thesis — but whether the commercialization timeline holds will be the real test of this strategic pivot.
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