TSMC Advances Multiple Arizona Fabs Simultaneously, 2nm Capacity to Account for 30% of Global Output
0xBroomberg
TSMC's Arizona site has entered a four-fab parallel build-out, with 2nm and below capacity set to account for roughly 30% of the company's global total — positioning the U.S. as TSMC's most important advanced manufacturing base outside Taiwan.
The first fab is already profitable — what does that prove?
Fab 1 (P1) runs 4nm and has reached volume production, already contributing profit.
Chairman C.C. Wei said P1 yields now match those at TSMC's Taiwan fabs. This means → the biggest question hanging over offshore expansion — whether cost and efficiency can catch up with the home base — has a preliminary answer: yes.
In plain terms = P1 isn't just "able to produce." It produces, sells, and earns. That baseline is the confidence foundation for everything that follows.
Where do the next fabs stand on the timeline?
P2: structural shell complete; equipment move-in starts Q4 2026; 2nm mass production pulled forward to H2 2027.
P3: equipment move-in set for September 2027; mass production target H2 2028.
P4: site grading and groundwork under way — the earliest stage. This means → the four fabs are staggered in a pipeline, not built one after another. Construction runs in parallel.
How is the process roadmap laid out?
P2 through P4 will run 2nm and A16 nodes; the longer-term P5 and P6 are slated for A14 and beyond.
TSMC has raised its total U.S. investment to $265 billion, spanning 2nm, A16, and A14 across multiple generations.
Under this plan, Arizona's 2nm-and-below capacity will represent roughly 30% of TSMC's global total — moving toward the Trump administration's goal of U.S. capacity exceeding half. This reflects a structural shift from "Taiwan-centric with offshore pilots" toward a genuine dual-hub model.
Why does advanced packaging need to be built alongside?
Advanced packaging fab AP1 will begin Phase 2 infrastructure and equipment installation in late 2027, with mass production possible by H2 2028.
Initial capabilities include SoIC — stacking multiple chips vertically — and CoWoS — placing chips and high-bandwidth memory side by side in one package — both aimed at AI chip demand.
In plain terms = wafer fabs alone aren't enough. AI chips require multiple dies "assembled" together before they function. Without packaging capacity keeping pace, wafer output can't become finished product.
What is the biggest uncertainty in this plan?
Amkor, Intel, and Micron are also expanding in Arizona and elsewhere in the U.S., driving sustained demand for local engineers and construction talent.
Whether build-out stays on schedule hinges on three variables: local engineering labor supply, equipment lead times, and shifts in AI market demand.
This means → TSMC's U.S. blueprint is drawn. Whether it delivers on time depends not on technology but on three real-world constraints: people, equipment, and market conditions.
Content is for reference only, not financial advice.