TSMC CoWoS Capacity to Double to 260K Wafers per Month by 2028
nashnova research
TSMC plans to raise CoWoS advanced-packaging capacity from roughly 70,000 wafers per month today to 260,000 by end-2028 — nearly a fourfold increase in three years. This means → the real bottleneck in AI chips is shifting from making them to packaging them, and the capacity arms race is just getting started.
What is CoWoS, and why is it choking AI chip supply?
CoWoS — chip-on-wafer-on-substrate — is TSMC's 2.5D packaging technology. It places a GPU or ASIC side-by-side with HBM memory (high-bandwidth memory, the ultra-fast data pool AI chips need) on a single silicon interposer, connected by dense through-silicon vias.
In plain terms = traditional packaging solders components onto a board and wires them up; CoWoS puts them on the same tabletop, cutting distance, boosting speed, and lowering power draw.
Nvidia's Blackwell GPUs, AMD's MI-series accelerators, and other high-end AI chips all require CoWoS packaging to ship. A chip that's fabricated but can't be packaged is a chip that doesn't exist.
How much capacity is being added, and where?
TSMC's CoWoS monthly-capacity roadmap: ~70K wafers in 2025 → ~130K in 2026 → 260K by end-2028 — nearly 4× in three years.
The buildout is split between two sites: the Arizona fab in the U.S. and the AP7 plant in Taiwan. But Arizona can only fabricate chips today — packaging is still in Taiwan. Finished wafers must be airfreighted back for CoWoS processing.
This reflects a reality often overlooked: advanced packaging is even more geographically concentrated than chip fabrication, and Taiwan's grip on packaging may be tighter than its grip on manufacturing.
Package sizes keep growing — how big are we talking?
TSMC is already mass-producing the world's largest CoWoS at 5.5× reticle size, with yields above 98%.
In plain terms = reticle size is the yardstick for package area. A 5.5× package is 5.5 times the area of a standard chip — room for more processors and more memory on one substrate.
Next milestones: a 14× reticle version integrating 20 HBM stacks enters mass production in 2028; a version exceeding 14× with 24 HBM stacks is slated for 2029. In parallel, TSMC is piloting panel-level packaging — CoPoS — targeting volume production as early as 2028–2029.
Who is competing for CoWoS capacity, and how is the mix shifting?
Morgan Stanley's supply-chain survey projects total CoWoS wafer demand from top customers at ~1.384 million in 2026, rising to ~2.682 million in 2027 — roughly 94% growth.
Nvidia remains the single largest customer: ~780K wafers in 2026 → ~1.2 million in 2027. But its share drops from ~56% to ~45%. This means → other players are growing faster, gradually diluting Nvidia's dominance.
The three fastest risers: AMD surges from 130K to 530K wafers (+300%, driven by MI-series accelerator ramp and chiplet adoption); MediaTek leaps from 40K to 180K (the highest growth rate among top clients, fueled by Google TPU-related ASIC work); Broadcom is projected at 484K in 2027 but drops to third, overtaken by AMD.
Who picks up the demand TSMC can't fill?
TSMC's CoWoS lines are chronically overbooked, pushing UMC, Amkor, and ASE to accelerate their own buildouts. By end-2027, non-TSMC monthly capacity is projected to reach roughly 80K wafers.
UBS estimates total industry CoWoS capacity will grow from ~160K wafers/month at end-2026 to ~250K at end-2027 — a ~56% jump in one year.
Intel's EMIB-T technology — which uses organic-substrate "bridge" interconnects instead of a silicon interposer, a fundamentally different architecture from CoWoS — is also gaining traction. Analyst estimates put EMIB-T capacity at ~15K–20K wafers/month in 2027 and ~40K–45K in 2028, with cloud giants like Google and Amazon as the natural customers for their custom AI chips.
Where does this arms race end?
TSMC's equipment supply-chain orders now have visibility extending to 2030. This means → the advanced-packaging buildout will not slow for at least five more years.
In plain terms = when equipment orders are booked half a decade out, the industry consensus is that demand has not peaked — and today's capacity gap is just the starting point.
This reflects a deeper shift: the real battlefield of the AI chip race is moving from "who can design the most powerful chip" to "who can package and mass-produce it." Packaging has become the defining bottleneck in AI hardware.
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