TSMC Executive: 3D IC Software and Substrates Are Critical Gaps in the Supply Chain
nashnova research
TSMC's packaging VP Jun He told a 3DIC summit that the bottleneck in 3D IC is not hardware but software tools and packaging substrates — putting EDA vendors and advanced substrate makers at the front of demand.
Where does TSMC see the bottleneck?
Jun He, TSMC's VP of advanced packaging, spoke at the SEMI 3DICAMA Global Summit on September 1. His core message: the constraint in 3D IC — stacking multiple chip layers vertically — is not fabrication equipment but two supporting links: software tools and packaging substrates.
This means → the tightest point in the supply chain has shifted from "machines that make chips" to "software that designs how chips stack" and "substrates that carry the stacked chips."
In plain terms = the hardware can be built, but the design and mounting steps cannot keep up.
What exactly is the software gap?
The software tools He referred to are mainly EDA/design software — specialized programs that let engineers draw chip circuits and simulate performance on a computer.
3D stacking is far more complex than traditional flat chips — signal integrity, thermal management, and mechanical stress between layers all need new modeling, and current tools have not fully caught up.
This means → EDA vendors such as Synopsys and Cadence face direct demand pull. Whoever closes this gap first locks in a critical ecosystem position.
What about the substrate gap?
Packaging substrates — the "base board" that carries a chip and connects it to the circuit board — are the other choke point for 3D IC deployment.
As chip layers multiply, demands on substrate wiring density and heat dissipation rise sharply. Both capacity and technical barriers for advanced substrates are climbing.
This reflects a broader reality: 3D IC is not just a chip-fabrication challenge — the entire supply chain must upgrade in parallel.
What does this mean for investors?
He's assessment represents TSMC's official view: advanced packaging has enormous commercial potential, but software and substrates are the key obstacles to scaling.
This means → within TSMC's 3D IC ecosystem, hardware equipment is a relatively secondary bottleneck. EDA software vendors and advanced substrate suppliers stand at the front line of demand.
One caveat: the original Digitimes report is paywalled. He's full remarks on specific technical specifications and supplier partnerships have not been publicly disclosed — worth tracking as more details emerge.
市场有风险，内容仅供研究参考，不构成投资建议。